--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone V" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=2 LPM_WIDTH=25 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 21.1 cbx_lpm_mux 2022:06:23:22:03:45:SJ cbx_mgl 2022:06:23:22:04:21:SJ  VERSION_END


-- Copyright (C) 2022  Intel Corporation. All rights reserved.
--  Your use of Intel Corporation's design tools, logic functions 
--  and other software and tools, and any partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Intel Program License 
--  Subscription Agreement, the Intel Quartus Prime License Agreement,
--  the Intel FPGA IP License Agreement, or other applicable license
--  agreement, including, without limitation, that your use is for
--  the sole purpose of programming logic devices manufactured by
--  Intel and sold by Intel or its authorized distributors.  Please
--  refer to the applicable agreement for further details, at
--  https://fpgasoftware.intel.com/eula.



--synthesis_resources = lut 9 
SUBDESIGN mux_flc
( 
	data[49..0]	:	input;
	result[24..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE
	l1_w0_n0_mux_dataout	:	WIRE;
	l1_w10_n0_mux_dataout	:	WIRE;
	l1_w11_n0_mux_dataout	:	WIRE;
	l1_w12_n0_mux_dataout	:	WIRE;
	l1_w13_n0_mux_dataout	:	WIRE;
	l1_w14_n0_mux_dataout	:	WIRE;
	l1_w15_n0_mux_dataout	:	WIRE;
	l1_w16_n0_mux_dataout	:	WIRE;
	l1_w17_n0_mux_dataout	:	WIRE;
	l1_w18_n0_mux_dataout	:	WIRE;
	l1_w19_n0_mux_dataout	:	WIRE;
	l1_w1_n0_mux_dataout	:	WIRE;
	l1_w20_n0_mux_dataout	:	WIRE;
	l1_w21_n0_mux_dataout	:	WIRE;
	l1_w22_n0_mux_dataout	:	WIRE;
	l1_w23_n0_mux_dataout	:	WIRE;
	l1_w24_n0_mux_dataout	:	WIRE;
	l1_w2_n0_mux_dataout	:	WIRE;
	l1_w3_n0_mux_dataout	:	WIRE;
	l1_w4_n0_mux_dataout	:	WIRE;
	l1_w5_n0_mux_dataout	:	WIRE;
	l1_w6_n0_mux_dataout	:	WIRE;
	l1_w7_n0_mux_dataout	:	WIRE;
	l1_w8_n0_mux_dataout	:	WIRE;
	l1_w9_n0_mux_dataout	:	WIRE;
	data_wire[49..0]	: WIRE;
	result_wire_ext[24..0]	: WIRE;
	sel_wire[0..0]	: WIRE;

BEGIN 
	l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[0..0];
	l1_w10_n0_mux_dataout = sel_wire[0..0] & data_wire[35..35] # !(sel_wire[0..0]) & data_wire[10..10];
	l1_w11_n0_mux_dataout = sel_wire[0..0] & data_wire[36..36] # !(sel_wire[0..0]) & data_wire[11..11];
	l1_w12_n0_mux_dataout = sel_wire[0..0] & data_wire[37..37] # !(sel_wire[0..0]) & data_wire[12..12];
	l1_w13_n0_mux_dataout = sel_wire[0..0] & data_wire[38..38] # !(sel_wire[0..0]) & data_wire[13..13];
	l1_w14_n0_mux_dataout = sel_wire[0..0] & data_wire[39..39] # !(sel_wire[0..0]) & data_wire[14..14];
	l1_w15_n0_mux_dataout = sel_wire[0..0] & data_wire[40..40] # !(sel_wire[0..0]) & data_wire[15..15];
	l1_w16_n0_mux_dataout = sel_wire[0..0] & data_wire[41..41] # !(sel_wire[0..0]) & data_wire[16..16];
	l1_w17_n0_mux_dataout = sel_wire[0..0] & data_wire[42..42] # !(sel_wire[0..0]) & data_wire[17..17];
	l1_w18_n0_mux_dataout = sel_wire[0..0] & data_wire[43..43] # !(sel_wire[0..0]) & data_wire[18..18];
	l1_w19_n0_mux_dataout = sel_wire[0..0] & data_wire[44..44] # !(sel_wire[0..0]) & data_wire[19..19];
	l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[1..1];
	l1_w20_n0_mux_dataout = sel_wire[0..0] & data_wire[45..45] # !(sel_wire[0..0]) & data_wire[20..20];
	l1_w21_n0_mux_dataout = sel_wire[0..0] & data_wire[46..46] # !(sel_wire[0..0]) & data_wire[21..21];
	l1_w22_n0_mux_dataout = sel_wire[0..0] & data_wire[47..47] # !(sel_wire[0..0]) & data_wire[22..22];
	l1_w23_n0_mux_dataout = sel_wire[0..0] & data_wire[48..48] # !(sel_wire[0..0]) & data_wire[23..23];
	l1_w24_n0_mux_dataout = sel_wire[0..0] & data_wire[49..49] # !(sel_wire[0..0]) & data_wire[24..24];
	l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[2..2];
	l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[3..3];
	l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[4..4];
	l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[5..5];
	l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[6..6];
	l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[32..32] # !(sel_wire[0..0]) & data_wire[7..7];
	l1_w8_n0_mux_dataout = sel_wire[0..0] & data_wire[33..33] # !(sel_wire[0..0]) & data_wire[8..8];
	l1_w9_n0_mux_dataout = sel_wire[0..0] & data_wire[34..34] # !(sel_wire[0..0]) & data_wire[9..9];
	data_wire[] = ( data[]);
	result[] = result_wire_ext[];
	result_wire_ext[] = ( l1_w24_n0_mux_dataout, l1_w23_n0_mux_dataout, l1_w22_n0_mux_dataout, l1_w21_n0_mux_dataout, l1_w20_n0_mux_dataout, l1_w19_n0_mux_dataout, l1_w18_n0_mux_dataout, l1_w17_n0_mux_dataout, l1_w16_n0_mux_dataout, l1_w15_n0_mux_dataout, l1_w14_n0_mux_dataout, l1_w13_n0_mux_dataout, l1_w12_n0_mux_dataout, l1_w11_n0_mux_dataout, l1_w10_n0_mux_dataout, l1_w9_n0_mux_dataout, l1_w8_n0_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n0_mux_dataout);
	sel_wire[] = ( sel[0..0]);
END;
--VALID FILE
