Core: D5M_QSYS_mem_if_lpddr2_emif_p0 - Instance: u0|mem_if_lpddr2_emif
Path, Setup Margin, Hold Margin
"Address Command (Slow 1100mV 85C Model)",0.363,0.44
"Bus Turnaround Time (Slow 1100mV 85C Model)",9.526,--
"Core (Slow 1100mV 85C Model)",-0.551,0.32
"Core Recovery/Removal (Slow 1100mV 85C Model)",-0.615,0.481
"DQS vs CK (Slow 1100mV 85C Model)",0.85,0.857
"Read Capture (Slow 1100mV 85C Model)",0.334,0.268
"Read Resync (Slow 1100mV 85C Model)",1.0,1.0
"Write (Slow 1100mV 85C Model)",0.176,0.3
"Address Command (Slow 1100mV 0C Model)",0.344,0.431
"Bus Turnaround Time (Slow 1100mV 0C Model)",9.566,--
"Core (Slow 1100mV 0C Model)",-0.651,0.314
"Core Recovery/Removal (Slow 1100mV 0C Model)",-0.597,0.34
"DQS vs CK (Slow 1100mV 0C Model)",0.886,0.894
"Read Capture (Slow 1100mV 0C Model)",0.34,0.274
"Read Resync (Slow 1100mV 0C Model)",1.0,1.0
"Write (Slow 1100mV 0C Model)",0.192,0.31
"Address Command (Fast 1100mV 85C Model)",0.291,0.279
"Bus Turnaround Time (Fast 1100mV 85C Model)",9.942,--
"Core (Fast 1100mV 85C Model)",1.709,-0.21
"Core Recovery/Removal (Fast 1100mV 85C Model)",2.655,0.226
"DQS vs CK (Fast 1100mV 85C Model)",1.267,1.251
"Read Capture (Fast 1100mV 85C Model)",0.514,0.448
"Read Resync (Fast 1100mV 85C Model)",1.0,1.0
"Write (Fast 1100mV 85C Model)",0.356,0.356
"Address Command (Fast 1100mV 0C Model)",0.261,0.29
"Bus Turnaround Time (Fast 1100mV 0C Model)",9.937,--
"Core (Fast 1100mV 0C Model)",1.733,-0.285
"Core Recovery/Removal (Fast 1100mV 0C Model)",2.877,0.166
"DQS vs CK (Fast 1100mV 0C Model)",1.263,1.257
"Read Capture (Fast 1100mV 0C Model)",0.515,0.449
"Read Resync (Fast 1100mV 0C Model)",1.0,1.0
"Write (Fast 1100mV 0C Model)",0.338,0.358
