Info (10281): Verilog HDL Declaration information at D5M_QSYS_id_router_003.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_id_router_003.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_id_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_id_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_addr_router_003.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_addr_router_003.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_addr_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_addr_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_id_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_id_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_addr_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_addr_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_rdwr_data_tmg.v(114): object "i" differs only in case from object "I" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(60): object "CFG_CAS_WR_LAT" differs only in case from object "cfg_cas_wr_lat" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(61): object "CFG_ADD_LAT" differs only in case from object "cfg_add_lat" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(62): object "CFG_TCL" differs only in case from object "cfg_tcl" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(63): object "CFG_BURST_LENGTH" differs only in case from object "cfg_burst_length" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(64): object "CFG_TRRD" differs only in case from object "cfg_trrd" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(65): object "CFG_TFAW" differs only in case from object "cfg_tfaw" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(66): object "CFG_TRFC" differs only in case from object "cfg_trfc" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(67): object "CFG_TREFI" differs only in case from object "cfg_trefi" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(68): object "CFG_TRCD" differs only in case from object "cfg_trcd" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(69): object "CFG_TRP" differs only in case from object "cfg_trp" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(70): object "CFG_TWR" differs only in case from object "cfg_twr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(71): object "CFG_TWTR" differs only in case from object "cfg_twtr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(72): object "CFG_TRTP" differs only in case from object "cfg_trtp" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(73): object "CFG_TRAS" differs only in case from object "cfg_tras" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(74): object "CFG_TRC" differs only in case from object "cfg_trc" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(75): object "CFG_AUTO_PD_CYCLES" differs only in case from object "cfg_auto_pd_cycles" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(78): object "CFG_ADDR_ORDER" differs only in case from object "cfg_addr_order" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(79): object "CFG_REORDER_DATA" differs only in case from object "cfg_reorder_data" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(80): object "CFG_STARVE_LIMIT" differs only in case from object "cfg_starve_limit" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(33): object "CFG_COL_ADDR_WIDTH" differs only in case from object "cfg_col_addr_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(32): object "CFG_ROW_ADDR_WIDTH" differs only in case from object "cfg_row_addr_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(34): object "CFG_BANK_ADDR_WIDTH" differs only in case from object "cfg_bank_addr_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(31): object "CFG_CS_ADDR_WIDTH" differs only in case from object "cfg_cs_addr_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(36): object "CFG_ENABLE_ECC" differs only in case from object "cfg_enable_ecc" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(37): object "CFG_ENABLE_AUTO_CORR" differs only in case from object "cfg_enable_auto_corr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_csr.v(38): object "CFG_REGDIMM_ENABLE" differs only in case from object "cfg_regdimm_enable" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_ecc_encoder_decoder_wrapper.v(20): object "CFG_LOCAL_DATA_WIDTH" differs only in case from object "cfg_local_data_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_ecc_encoder_decoder_wrapper.v(158): object "CFG_LOCAL_DM_WIDTH" differs only in case from object "cfg_local_dm_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller.v(43): object "CFG_OUTPUT_REGD" differs only in case from object "cfg_output_regd" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(150): object "CFG_TYPE" differs only in case from object "cfg_type" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(152): object "CFG_BURST_LENGTH" differs only in case from object "cfg_burst_length" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(157): object "CFG_ADDR_ORDER" differs only in case from object "cfg_addr_order" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(271): object "CFG_ENABLE_ECC" differs only in case from object "cfg_enable_ecc" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(272): object "CFG_ENABLE_AUTO_CORR" differs only in case from object "cfg_enable_auto_corr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(182): object "CFG_GEN_SBE" differs only in case from object "cfg_gen_sbe" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(183): object "CFG_GEN_DBE" differs only in case from object "cfg_gen_dbe" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(154): object "CFG_REORDER_DATA" differs only in case from object "cfg_reorder_data" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(305): object "CFG_USER_RFSH" differs only in case from object "cfg_user_rfsh" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(306): object "CFG_REGDIMM_ENABLE" differs only in case from object "cfg_regdimm_enable" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(307): object "CFG_ENABLE_BURST_INTERRUPT" differs only in case from object "cfg_enable_burst_interrupt" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(308): object "CFG_ENABLE_BURST_TERMINATE" differs only in case from object "cfg_enable_burst_terminate" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(203): object "CFG_ENABLE_DQS_TRACKING" differs only in case from object "cfg_enable_dqs_tracking" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(303): object "CFG_OUTPUT_REGD" differs only in case from object "cfg_output_regd" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(199): object "CFG_ENABLE_NO_DM" differs only in case from object "cfg_enable_no_dm" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(274): object "CFG_ENABLE_ECC_CODE_OVERWRITES" differs only in case from object "cfg_enable_ecc_code_overwrites" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(255): object "CFG_CAS_WR_LAT" differs only in case from object "cfg_cas_wr_lat" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(256): object "CFG_ADD_LAT" differs only in case from object "cfg_add_lat" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(257): object "CFG_TCL" differs only in case from object "cfg_tcl" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(258): object "CFG_TRRD" differs only in case from object "cfg_trrd" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(259): object "CFG_TFAW" differs only in case from object "cfg_tfaw" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(260): object "CFG_TRFC" differs only in case from object "cfg_trfc" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(261): object "CFG_TREFI" differs only in case from object "cfg_trefi" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(262): object "CFG_TRCD" differs only in case from object "cfg_trcd" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(263): object "CFG_TRP" differs only in case from object "cfg_trp" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(264): object "CFG_TWR" differs only in case from object "cfg_twr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(265): object "CFG_TWTR" differs only in case from object "cfg_twtr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(266): object "CFG_TRTP" differs only in case from object "cfg_trtp" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(267): object "CFG_TRAS" differs only in case from object "cfg_tras" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(268): object "CFG_TRC" differs only in case from object "cfg_trc" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(269): object "CFG_AUTO_PD_CYCLES" differs only in case from object "cfg_auto_pd_cycles" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(174): object "CFG_SELF_RFSH_EXIT_CYCLES" differs only in case from object "cfg_self_rfsh_exit_cycles" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(175): object "CFG_PDN_EXIT_CYCLES" differs only in case from object "cfg_pdn_exit_cycles" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(176): object "CFG_POWER_SAVING_EXIT_CYCLES" differs only in case from object "cfg_power_saving_exit_cycles" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(177): object "CFG_MEM_CLK_ENTRY_CYCLES" differs only in case from object "cfg_mem_clk_entry_cycles" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(270): object "CFG_TMRD" differs only in case from object "cfg_tmrd" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(251): object "CFG_COL_ADDR_WIDTH" differs only in case from object "cfg_col_addr_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(252): object "CFG_ROW_ADDR_WIDTH" differs only in case from object "cfg_row_addr_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(253): object "CFG_BANK_ADDR_WIDTH" differs only in case from object "cfg_bank_addr_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(254): object "CFG_CS_ADDR_WIDTH" differs only in case from object "cfg_cs_addr_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(184): object "CFG_ENABLE_INTR" differs only in case from object "cfg_enable_intr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(185): object "CFG_MASK_SBE_INTR" differs only in case from object "cfg_mask_sbe_intr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(186): object "CFG_MASK_DBE_INTR" differs only in case from object "cfg_mask_dbe_intr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(188): object "CFG_CLR_INTR" differs only in case from object "cfg_clr_intr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(275): object "CFG_CAL_REQ" differs only in case from object "cfg_cal_req" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(276): object "CFG_EXTRA_CTL_CLK_ACT_TO_RDWR" differs only in case from object "cfg_extra_ctl_clk_act_to_rdwr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(277): object "CFG_EXTRA_CTL_CLK_ACT_TO_PCH" differs only in case from object "cfg_extra_ctl_clk_act_to_pch" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(278): object "CFG_EXTRA_CTL_CLK_ACT_TO_ACT" differs only in case from object "cfg_extra_ctl_clk_act_to_act" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(279): object "CFG_EXTRA_CTL_CLK_RD_TO_RD" differs only in case from object "cfg_extra_ctl_clk_rd_to_rd" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(280): object "CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" differs only in case from object "cfg_extra_ctl_clk_rd_to_rd_diff_chip" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(281): object "CFG_EXTRA_CTL_CLK_RD_TO_WR" differs only in case from object "cfg_extra_ctl_clk_rd_to_wr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(282): object "CFG_EXTRA_CTL_CLK_RD_TO_WR_BC" differs only in case from object "cfg_extra_ctl_clk_rd_to_wr_bc" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(283): object "CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" differs only in case from object "cfg_extra_ctl_clk_rd_to_wr_diff_chip" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(284): object "CFG_EXTRA_CTL_CLK_RD_TO_PCH" differs only in case from object "cfg_extra_ctl_clk_rd_to_pch" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(285): object "CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID" differs only in case from object "cfg_extra_ctl_clk_rd_ap_to_valid" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(286): object "CFG_EXTRA_CTL_CLK_WR_TO_WR" differs only in case from object "cfg_extra_ctl_clk_wr_to_wr" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(287): object "CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" differs only in case from object "cfg_extra_ctl_clk_wr_to_wr_diff_chip" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(288): object "CFG_EXTRA_CTL_CLK_WR_TO_RD" differs only in case from object "cfg_extra_ctl_clk_wr_to_rd" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(289): object "CFG_EXTRA_CTL_CLK_WR_TO_RD_BC" differs only in case from object "cfg_extra_ctl_clk_wr_to_rd_bc" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(290): object "CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" differs only in case from object "cfg_extra_ctl_clk_wr_to_rd_diff_chip" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(291): object "CFG_EXTRA_CTL_CLK_WR_TO_PCH" differs only in case from object "cfg_extra_ctl_clk_wr_to_pch" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(292): object "CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID" differs only in case from object "cfg_extra_ctl_clk_wr_ap_to_valid" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(293): object "CFG_EXTRA_CTL_CLK_PCH_TO_VALID" differs only in case from object "cfg_extra_ctl_clk_pch_to_valid" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(294): object "CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" differs only in case from object "cfg_extra_ctl_clk_pch_all_to_valid" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(295): object "CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" differs only in case from object "cfg_extra_ctl_clk_act_to_act_diff_bank" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(296): object "CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" differs only in case from object "cfg_extra_ctl_clk_four_act_to_act" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(297): object "CFG_EXTRA_CTL_CLK_ARF_TO_VALID" differs only in case from object "cfg_extra_ctl_clk_arf_to_valid" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(298): object "CFG_EXTRA_CTL_CLK_PDN_TO_VALID" differs only in case from object "cfg_extra_ctl_clk_pdn_to_valid" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(299): object "CFG_EXTRA_CTL_CLK_SRF_TO_VALID" differs only in case from object "cfg_extra_ctl_clk_srf_to_valid" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(300): object "CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" differs only in case from object "cfg_extra_ctl_clk_srf_to_zq_cal" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(301): object "CFG_EXTRA_CTL_CLK_ARF_PERIOD" differs only in case from object "cfg_extra_ctl_clk_arf_period" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(302): object "CFG_EXTRA_CTL_CLK_PDN_PERIOD" differs only in case from object "cfg_extra_ctl_clk_pdn_period" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(156): object "CFG_STARVE_LIMIT" differs only in case from object "cfg_starve_limit" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(193): object "CFG_WRITE_ODT_CHIP" differs only in case from object "cfg_write_odt_chip" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(194): object "CFG_READ_ODT_CHIP" differs only in case from object "cfg_read_odt_chip" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(151): object "CFG_INTERFACE_WIDTH" differs only in case from object "cfg_interface_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(153): object "CFG_DEVICE_WIDTH" differs only in case from object "cfg_device_width" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(172): object "CFG_TCCD" differs only in case from object "cfg_tccd" in the same scope
Info (10281): Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(304): object "CFG_MASK_CORR_DROPPED_INTR" differs only in case from object "cfg_mask_corr_dropped_intr" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_addr_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_addr_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_addr_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_addr_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_addr_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_addr_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_addr_router_003.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_addr_router_003.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_addr_router_004.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_addr_router_004.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_id_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_id_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_id_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_id_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_id_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_id_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_id_router_003.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_id_router_003.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_id_router_004.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at D5M_QSYS_mem_if_lpddr2_emif_s0_id_router_004.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at rw_manager_core.sv(71): object "RATE" differs only in case from object "rate" in the same scope
Warning (10268): Verilog HDL information at sequencer_phy_mgr.sv(398): always construct contains both blocking and non-blocking assignments
Info (10281): Verilog HDL Declaration information at alt_vipitc130_IS2Vid.sv(99): object "TRS" differs only in case from object "trs" in the same scope
Info (10281): Verilog HDL Declaration information at alt_vipitc130_IS2Vid.sv(63): object "INTERLACED" differs only in case from object "interlaced" in the same scope
Info (10281): Verilog HDL Declaration information at alt_vipitc130_IS2Vid.sv(64): object "AP_LINE" differs only in case from object "ap_line" in the same scope
Info (10281): Verilog HDL Declaration information at alt_vipitc130_IS2Vid.sv(72): object "H_BLANK" differs only in case from object "h_blank" in the same scope
Info (10281): Verilog HDL Declaration information at alt_vipitc130_IS2Vid.sv(82): object "F_RISING_EDGE" differs only in case from object "f_rising_edge" in the same scope
Info (10281): Verilog HDL Declaration information at alt_vipitc130_IS2Vid.sv(83): object "F_FALLING_EDGE" differs only in case from object "f_falling_edge" in the same scope
Warning (10268): Verilog HDL information at alt_vipitc130_IS2Vid_mode_banks.sv(413): always construct contains both blocking and non-blocking assignments
Info (10281): Verilog HDL Declaration information at alt_vipitc130_IS2Vid_mode_banks.sv(8): object "INTERLACED" differs only in case from object "interlaced" in the same scope
Info (10281): Verilog HDL Declaration information at alt_vipitc130_IS2Vid_mode_banks.sv(21): object "AP_LINE" differs only in case from object "ap_line" in the same scope
Info (10281): Verilog HDL Declaration information at alt_vipitc130_IS2Vid_mode_banks.sv(23): object "F_RISING_EDGE" differs only in case from object "f_rising_edge" in the same scope
Info (10281): Verilog HDL Declaration information at alt_vipitc130_IS2Vid_mode_banks.sv(24): object "F_FALLING_EDGE" differs only in case from object "f_falling_edge" in the same scope
Info (10281): Verilog HDL Declaration information at alt_vipitc130_common_generic_count.v(3): object "MAX_COUNT" differs only in case from object "max_count" in the same scope
Info (10281): Verilog HDL Declaration information at alt_vipitc130_common_generic_count.v(4): object "RESET_VALUE" differs only in case from object "reset_value" in the same scope
Warning (10268): Verilog HDL information at alt_vipitc130_common_sync_generation.v(59): always construct contains both blocking and non-blocking assignments
