// TR4_QSYS_mem_if_lpddr2_emif.v

// This file was auto-generated from alt_mem_if_lpddr2_emif_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 13.0sp1 232 at 2013.07.08.11:47:50

`timescale 1 ps / 1 ps
module TR4_QSYS_mem_if_lpddr2_emif (
		input  wire         pll_ref_clk,               //      pll_ref_clk.clk
		input  wire         global_reset_n,            //     global_reset.reset_n
		input  wire         soft_reset_n,              //       soft_reset.reset_n
		output wire         afi_clk,                   //          afi_clk.clk
		output wire         afi_half_clk,              //     afi_half_clk.clk
		output wire         afi_reset_n,               //        afi_reset.reset_n
		output wire         afi_reset_export_n,        // afi_reset_export.reset_n
		output wire [9:0]   mem_ca,                    //           memory.mem_ca
		output wire [0:0]   mem_ck,                    //                 .mem_ck
		output wire [0:0]   mem_ck_n,                  //                 .mem_ck_n
		output wire [0:0]   mem_cke,                   //                 .mem_cke
		output wire [0:0]   mem_cs_n,                  //                 .mem_cs_n
		output wire [3:0]   mem_dm,                    //                 .mem_dm
		inout  wire [31:0]  mem_dq,                    //                 .mem_dq
		inout  wire [3:0]   mem_dqs,                   //                 .mem_dqs
		inout  wire [3:0]   mem_dqs_n,                 //                 .mem_dqs_n
		output wire         avl_ready,                 //              avl.waitrequest_n
		input  wire         avl_burstbegin,            //                 .beginbursttransfer
		input  wire [23:0]  avl_addr,                  //                 .address
		output wire         avl_rdata_valid,           //                 .readdatavalid
		output wire [127:0] avl_rdata,                 //                 .readdata
		input  wire [127:0] avl_wdata,                 //                 .writedata
		input  wire [15:0]  avl_be,                    //                 .byteenable
		input  wire         avl_read_req,              //                 .read
		input  wire         avl_write_req,             //                 .write
		input  wire [2:0]   avl_size,                  //                 .burstcount
		output wire         local_init_done,           //           status.local_init_done
		output wire         local_cal_success,         //                 .local_cal_success
		output wire         local_cal_fail,            //                 .local_cal_fail
		input  wire         oct_rzqin,                 //              oct.rzqin
		output wire         pll_mem_clk,               //      pll_sharing.pll_mem_clk
		output wire         pll_write_clk,             //                 .pll_write_clk
		output wire         pll_write_clk_pre_phy_clk, //                 .pll_write_clk_pre_phy_clk
		output wire         pll_addr_cmd_clk,          //                 .pll_addr_cmd_clk
		output wire         pll_locked,                //                 .pll_locked
		output wire         pll_avl_clk,               //                 .pll_avl_clk
		output wire         pll_config_clk,            //                 .pll_config_clk
		output wire         pll_mem_phy_clk,           //                 .pll_mem_phy_clk
		output wire         afi_phy_clk,               //                 .afi_phy_clk
		output wire         pll_avl_phy_clk            //                 .pll_avl_phy_clk
	);

	wire   [39:0] m0_phy_mux_afi_addr;                                               // m0:phy_mux_addr -> p0:afi_addr
	wire    [5:0] p0_afi_afi_wlat;                                                   // p0:afi_wlat -> m0:phy_mux_wlat
	wire    [1:0] m0_phy_mux_afi_rdata_en_full;                                      // m0:phy_mux_rdata_en_full -> p0:afi_rdata_en_full
	wire    [1:0] p0_afi_afi_rdata_valid;                                            // p0:afi_rdata_valid -> m0:phy_mux_rdata_valid
	wire    [1:0] m0_phy_mux_afi_cke;                                                // m0:phy_mux_cke -> p0:afi_cke
	wire    [1:0] m0_phy_mux_afi_cs_n;                                               // m0:phy_mux_cs_n -> p0:afi_cs_n
	wire  [127:0] m0_phy_mux_afi_wdata;                                              // m0:phy_mux_wdata -> p0:afi_wdata
	wire    [1:0] m0_phy_mux_afi_rdata_en;                                           // m0:phy_mux_rdata_en -> p0:afi_rdata_en
	wire          p0_afi_afi_cal_success;                                            // p0:afi_cal_success -> m0:phy_mux_cal_success
	wire    [5:0] p0_afi_afi_rlat;                                                   // p0:afi_rlat -> m0:phy_mux_rlat
	wire  [127:0] p0_afi_afi_rdata;                                                  // p0:afi_rdata -> m0:phy_mux_rdata
	wire    [7:0] m0_phy_mux_afi_wdata_valid;                                        // m0:phy_mux_wdata_valid -> p0:afi_wdata_valid
	wire          p0_afi_afi_cal_fail;                                               // p0:afi_cal_fail -> m0:phy_mux_cal_fail
	wire    [7:0] m0_phy_mux_afi_dqs_burst;                                          // m0:phy_mux_dqs_burst -> p0:afi_dqs_burst
	wire   [15:0] m0_phy_mux_afi_dm;                                                 // m0:phy_mux_dm -> p0:afi_dm
	wire    [5:0] m0_afi_afi_wlat;                                                   // m0:afi_wlat -> c0:afi_wlat
	wire    [1:0] m0_afi_afi_rdata_valid;                                            // m0:afi_rdata_valid -> c0:afi_rdata_valid
	wire          m0_afi_afi_cal_success;                                            // m0:afi_cal_success -> c0:afi_cal_success
	wire    [5:0] m0_afi_afi_rlat;                                                   // m0:afi_rlat -> c0:afi_rlat
	wire  [127:0] m0_afi_afi_rdata;                                                  // m0:afi_rdata -> c0:afi_rdata
	wire          m0_afi_afi_cal_fail;                                               // m0:afi_cal_fail -> c0:afi_cal_fail
	wire          p0_avl_clk_clk;                                                    // p0:avl_clk -> [dmaster:clk_clk, dmaster_master_translator:clk, s0:avl_clk, s0_seq_debug_translator:clk]
	wire          p0_avl_reset_reset;                                                // p0:avl_reset_n -> [dmaster:clk_reset_reset, dmaster_master_translator:reset, s0:avl_reset_n, s0_seq_debug_translator:reset]
	wire          p0_scc_clk_clk;                                                    // p0:scc_clk -> s0:scc_clk
	wire          p0_scc_reset_reset;                                                // p0:scc_reset_n -> s0:reset_n_scc_clk
	wire   [39:0] s0_afi_afi_addr;                                                   // s0:afi_addr -> m0:seq_mux_addr
	wire  [127:0] m0_seq_mux_afi_rdata;                                              // m0:seq_mux_rdata -> s0:afi_rdata
	wire    [1:0] m0_seq_mux_afi_rdata_valid;                                        // m0:seq_mux_rdata_valid -> s0:afi_rdata_valid
	wire    [1:0] s0_afi_afi_rdata_en_full;                                          // s0:afi_rdata_en_full -> m0:seq_mux_rdata_en_full
	wire    [7:0] s0_afi_afi_wdata_valid;                                            // s0:afi_wdata_valid -> m0:seq_mux_wdata_valid
	wire  [127:0] s0_afi_afi_wdata;                                                  // s0:afi_wdata -> m0:seq_mux_wdata
	wire    [1:0] s0_afi_afi_cs_n;                                                   // s0:afi_cs_n -> m0:seq_mux_cs_n
	wire    [1:0] s0_afi_afi_cke;                                                    // s0:afi_cke -> m0:seq_mux_cke
	wire    [1:0] s0_afi_afi_rdata_en;                                               // s0:afi_rdata_en -> m0:seq_mux_rdata_en
	wire    [7:0] s0_afi_afi_dqs_burst;                                              // s0:afi_dqs_burst -> m0:seq_mux_dqs_burst
	wire   [15:0] s0_afi_afi_dm;                                                     // s0:afi_dm -> m0:seq_mux_dm
	wire          s0_mux_sel_mux_sel;                                                // s0:phy_mux_sel -> m0:mux_sel
	wire          s0_phy_phy_cal_success;                                            // s0:phy_cal_success -> p0:phy_cal_success
	wire          p0_phy_phy_reset_n;                                                // p0:phy_reset_n -> s0:phy_reset_n
	wire          s0_phy_phy_cal_fail;                                               // s0:phy_cal_fail -> p0:phy_cal_fail
	wire    [3:0] s0_phy_phy_read_increment_vfifo_qr;                                // s0:phy_read_increment_vfifo_qr -> p0:phy_read_increment_vfifo_qr
	wire          p0_phy_phy_clk;                                                    // p0:phy_clk -> s0:phy_clk
	wire    [5:0] s0_phy_phy_afi_rlat;                                               // s0:phy_afi_rlat -> p0:phy_afi_rlat
	wire    [3:0] s0_phy_phy_read_increment_vfifo_hr;                                // s0:phy_read_increment_vfifo_hr -> p0:phy_read_increment_vfifo_hr
	wire    [3:0] s0_phy_phy_vfifo_rd_en_override;                                   // s0:phy_vfifo_rd_en_override -> p0:phy_vfifo_rd_en_override
	wire  [127:0] p0_phy_phy_read_fifo_q;                                            // p0:phy_read_fifo_q -> s0:phy_read_fifo_q
	wire    [4:0] s0_phy_phy_read_latency_counter;                                   // s0:phy_read_latency_counter -> p0:phy_read_latency_counter
	wire    [3:0] s0_phy_phy_read_fifo_reset;                                        // s0:phy_read_fifo_reset -> p0:phy_read_fifo_reset
	wire    [3:0] s0_phy_phy_read_increment_vfifo_fr;                                // s0:phy_read_increment_vfifo_fr -> p0:phy_read_increment_vfifo_fr
	wire   [31:0] s0_phy_phy_cal_debug_info;                                         // s0:phy_cal_debug_info -> p0:phy_cal_debug_info
	wire          s0_phy_phy_reset_mem_stable;                                       // s0:phy_reset_mem_stable -> p0:phy_reset_mem_stable
	wire    [5:0] s0_phy_phy_afi_wlat;                                               // s0:phy_afi_wlat -> p0:phy_afi_wlat
	wire    [7:0] p0_calib_calib_skip_steps;                                         // p0:calib_skip_steps -> s0:calib_skip_steps
	wire    [3:0] s0_scc_scc_dm_ena;                                                 // s0:scc_dm_ena -> p0:scc_dm_ena
	wire   [31:0] s0_scc_scc_dq_ena;                                                 // s0:scc_dq_ena -> p0:scc_dq_ena
	wire    [3:0] s0_scc_scc_dqs_ena;                                                // s0:scc_dqs_ena -> p0:scc_dqs_ena
	wire    [0:0] s0_scc_scc_upd;                                                    // s0:scc_upd -> p0:scc_upd
	wire    [3:0] p0_scc_capture_strobe_tracking;                                    // p0:capture_strobe_tracking -> s0:capture_strobe_tracking
	wire    [3:0] s0_scc_scc_dqs_io_ena;                                             // s0:scc_dqs_io_ena -> p0:scc_dqs_io_ena
	wire          s0_scc_scc_data;                                                   // s0:scc_data -> p0:scc_data
	wire    [0:0] s0_tracking_afi_seq_busy;                                          // s0:afi_seq_busy -> c0:afi_seq_busy
	wire          dmaster_master_reset_reset;                                        // dmaster:master_reset_reset -> p0:csr_soft_reset_req
	wire   [39:0] c0_afi_afi_addr;                                                   // c0:afi_addr -> m0:afi_addr
	wire          c0_afi_afi_cal_req;                                                // c0:afi_cal_req -> s0:afi_cal_req
	wire    [1:0] c0_afi_afi_rdata_en_full;                                          // c0:afi_rdata_en_full -> m0:afi_rdata_en_full
	wire    [1:0] c0_afi_afi_cke;                                                    // c0:afi_cke -> m0:afi_cke
	wire    [1:0] c0_afi_afi_cs_n;                                                   // c0:afi_cs_n -> m0:afi_cs_n
	wire  [127:0] c0_afi_afi_wdata;                                                  // c0:afi_wdata -> m0:afi_wdata
	wire    [1:0] c0_afi_afi_rdata_en;                                               // c0:afi_rdata_en -> m0:afi_rdata_en
	wire    [0:0] c0_afi_afi_mem_clk_disable;                                        // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
	wire          c0_afi_afi_init_req;                                               // c0:afi_init_req -> s0:afi_init_req
	wire    [7:0] c0_afi_afi_wdata_valid;                                            // c0:afi_wdata_valid -> m0:afi_wdata_valid
	wire    [0:0] c0_afi_afi_ctl_refresh_done;                                       // c0:afi_ctl_refresh_done -> s0:afi_ctl_refresh_done
	wire    [7:0] c0_afi_afi_dqs_burst;                                              // c0:afi_dqs_burst -> m0:afi_dqs_burst
	wire    [0:0] c0_afi_afi_ctl_long_idle;                                          // c0:afi_ctl_long_idle -> s0:afi_ctl_long_idle
	wire   [15:0] c0_afi_afi_dm;                                                     // c0:afi_dm -> m0:afi_dm
	wire   [15:0] oct0_oct_sharing_parallelterminationcontrol;                       // oct0:parallelterminationcontrol -> p0:parallelterminationcontrol
	wire   [15:0] oct0_oct_sharing_seriesterminationcontrol;                         // oct0:seriesterminationcontrol -> p0:seriesterminationcontrol
	wire          p0_dll_clk_clk;                                                    // p0:dll_clk -> dll0:clk
	wire          p0_dll_sharing_dll_pll_locked;                                     // p0:dll_pll_locked -> dll0:dll_pll_locked
	wire    [6:0] dll0_dll_sharing_dll_delayctrl;                                    // dll0:dll_delayctrl -> p0:dll_delayctrl
	wire          dmaster_master_waitrequest;                                        // dmaster_master_translator:av_waitrequest -> dmaster:master_waitrequest
	wire   [31:0] dmaster_master_writedata;                                          // dmaster:master_writedata -> dmaster_master_translator:av_writedata
	wire   [31:0] dmaster_master_address;                                            // dmaster:master_address -> dmaster_master_translator:av_address
	wire          dmaster_master_write;                                              // dmaster:master_write -> dmaster_master_translator:av_write
	wire          dmaster_master_read;                                               // dmaster:master_read -> dmaster_master_translator:av_read
	wire   [31:0] dmaster_master_readdata;                                           // dmaster_master_translator:av_readdata -> dmaster:master_readdata
	wire    [3:0] dmaster_master_byteenable;                                         // dmaster:master_byteenable -> dmaster_master_translator:av_byteenable
	wire          dmaster_master_readdatavalid;                                      // dmaster_master_translator:av_readdatavalid -> dmaster:master_readdatavalid
	wire          dmaster_master_translator_avalon_universal_master_0_waitrequest;   // s0_seq_debug_translator:uav_waitrequest -> dmaster_master_translator:uav_waitrequest
	wire    [2:0] dmaster_master_translator_avalon_universal_master_0_burstcount;    // dmaster_master_translator:uav_burstcount -> s0_seq_debug_translator:uav_burstcount
	wire   [31:0] dmaster_master_translator_avalon_universal_master_0_writedata;     // dmaster_master_translator:uav_writedata -> s0_seq_debug_translator:uav_writedata
	wire   [31:0] dmaster_master_translator_avalon_universal_master_0_address;       // dmaster_master_translator:uav_address -> s0_seq_debug_translator:uav_address
	wire          dmaster_master_translator_avalon_universal_master_0_lock;          // dmaster_master_translator:uav_lock -> s0_seq_debug_translator:uav_lock
	wire          dmaster_master_translator_avalon_universal_master_0_write;         // dmaster_master_translator:uav_write -> s0_seq_debug_translator:uav_write
	wire          dmaster_master_translator_avalon_universal_master_0_read;          // dmaster_master_translator:uav_read -> s0_seq_debug_translator:uav_read
	wire   [31:0] dmaster_master_translator_avalon_universal_master_0_readdata;      // s0_seq_debug_translator:uav_readdata -> dmaster_master_translator:uav_readdata
	wire          dmaster_master_translator_avalon_universal_master_0_debugaccess;   // dmaster_master_translator:uav_debugaccess -> s0_seq_debug_translator:uav_debugaccess
	wire    [3:0] dmaster_master_translator_avalon_universal_master_0_byteenable;    // dmaster_master_translator:uav_byteenable -> s0_seq_debug_translator:uav_byteenable
	wire          dmaster_master_translator_avalon_universal_master_0_readdatavalid; // s0_seq_debug_translator:uav_readdatavalid -> dmaster_master_translator:uav_readdatavalid
	wire          s0_seq_debug_translator_avalon_anti_slave_0_waitrequest;           // s0:seq_waitrequest -> s0_seq_debug_translator:av_waitrequest
	wire    [0:0] s0_seq_debug_translator_avalon_anti_slave_0_burstcount;            // s0_seq_debug_translator:av_burstcount -> s0:seq_burstcount
	wire   [31:0] s0_seq_debug_translator_avalon_anti_slave_0_writedata;             // s0_seq_debug_translator:av_writedata -> s0:seq_writedata
	wire   [31:0] s0_seq_debug_translator_avalon_anti_slave_0_address;               // s0_seq_debug_translator:av_address -> s0:seq_address
	wire          s0_seq_debug_translator_avalon_anti_slave_0_write;                 // s0_seq_debug_translator:av_write -> s0:seq_write
	wire          s0_seq_debug_translator_avalon_anti_slave_0_read;                  // s0_seq_debug_translator:av_read -> s0:seq_read
	wire   [31:0] s0_seq_debug_translator_avalon_anti_slave_0_readdata;              // s0:seq_readdata -> s0_seq_debug_translator:av_readdata
	wire          s0_seq_debug_translator_avalon_anti_slave_0_readdatavalid;         // s0:seq_readdatavalid -> s0_seq_debug_translator:av_readdatavalid
	wire    [3:0] s0_seq_debug_translator_avalon_anti_slave_0_byteenable;            // s0_seq_debug_translator:av_byteenable -> s0:seq_byteenable

	TR4_QSYS_mem_if_lpddr2_emif_pll0 pll0 (
		.global_reset_n            (global_reset_n),            // global_reset.reset_n
		.afi_clk                   (afi_clk),                   //      afi_clk.clk
		.afi_half_clk              (afi_half_clk),              // afi_half_clk.clk
		.pll_ref_clk               (pll_ref_clk),               //  pll_ref_clk.clk
		.pll_mem_clk               (pll_mem_clk),               //  pll_sharing.pll_mem_clk
		.pll_write_clk             (pll_write_clk),             //             .pll_write_clk
		.pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), //             .pll_write_clk_pre_phy_clk
		.pll_addr_cmd_clk          (pll_addr_cmd_clk),          //             .pll_addr_cmd_clk
		.pll_locked                (pll_locked),                //             .pll_locked
		.pll_avl_clk               (pll_avl_clk),               //             .pll_avl_clk
		.pll_config_clk            (pll_config_clk),            //             .pll_config_clk
		.pll_mem_phy_clk           (pll_mem_phy_clk),           //             .pll_mem_phy_clk
		.afi_phy_clk               (afi_phy_clk),               //             .afi_phy_clk
		.pll_avl_phy_clk           (pll_avl_phy_clk)            //             .pll_avl_phy_clk
	);

	TR4_QSYS_mem_if_lpddr2_emif_p0 p0 (
		.global_reset_n              (global_reset_n),                              //        global_reset.reset_n
		.soft_reset_n                (soft_reset_n),                                //          soft_reset.reset_n
		.csr_soft_reset_req          (dmaster_master_reset_reset),                  //  csr_soft_reset_req.reset
		.afi_reset_n                 (afi_reset_n),                                 //           afi_reset.reset_n
		.afi_reset_export_n          (afi_reset_export_n),                          //    afi_reset_export.reset_n
		.afi_clk                     (afi_clk),                                     //             afi_clk.clk
		.afi_half_clk                (afi_half_clk),                                //        afi_half_clk.clk
		.addr_cmd_clk                (),                                            //        addr_cmd_clk.clk
		.avl_clk                     (p0_avl_clk_clk),                              //             avl_clk.clk
		.avl_reset_n                 (p0_avl_reset_reset),                          //           avl_reset.reset_n
		.scc_clk                     (p0_scc_clk_clk),                              //             scc_clk.clk
		.scc_reset_n                 (p0_scc_reset_reset),                          //           scc_reset.reset_n
		.dll_clk                     (p0_dll_clk_clk),                              //             dll_clk.clk
		.afi_addr                    (m0_phy_mux_afi_addr),                         //                 afi.afi_addr
		.afi_cke                     (m0_phy_mux_afi_cke),                          //                    .afi_cke
		.afi_cs_n                    (m0_phy_mux_afi_cs_n),                         //                    .afi_cs_n
		.afi_dqs_burst               (m0_phy_mux_afi_dqs_burst),                    //                    .afi_dqs_burst
		.afi_wdata_valid             (m0_phy_mux_afi_wdata_valid),                  //                    .afi_wdata_valid
		.afi_wdata                   (m0_phy_mux_afi_wdata),                        //                    .afi_wdata
		.afi_dm                      (m0_phy_mux_afi_dm),                           //                    .afi_dm
		.afi_rdata                   (p0_afi_afi_rdata),                            //                    .afi_rdata
		.afi_rdata_en                (m0_phy_mux_afi_rdata_en),                     //                    .afi_rdata_en
		.afi_rdata_en_full           (m0_phy_mux_afi_rdata_en_full),                //                    .afi_rdata_en_full
		.afi_rdata_valid             (p0_afi_afi_rdata_valid),                      //                    .afi_rdata_valid
		.afi_cal_success             (p0_afi_afi_cal_success),                      //                    .afi_cal_success
		.afi_cal_fail                (p0_afi_afi_cal_fail),                         //                    .afi_cal_fail
		.afi_wlat                    (p0_afi_afi_wlat),                             //                    .afi_wlat
		.afi_rlat                    (p0_afi_afi_rlat),                             //                    .afi_rlat
		.phy_clk                     (p0_phy_phy_clk),                              //                 phy.phy_clk
		.phy_reset_n                 (p0_phy_phy_reset_n),                          //                    .phy_reset_n
		.phy_read_latency_counter    (s0_phy_phy_read_latency_counter),             //                    .phy_read_latency_counter
		.phy_afi_wlat                (s0_phy_phy_afi_wlat),                         //                    .phy_afi_wlat
		.phy_afi_rlat                (s0_phy_phy_afi_rlat),                         //                    .phy_afi_rlat
		.phy_read_increment_vfifo_fr (s0_phy_phy_read_increment_vfifo_fr),          //                    .phy_read_increment_vfifo_fr
		.phy_read_increment_vfifo_hr (s0_phy_phy_read_increment_vfifo_hr),          //                    .phy_read_increment_vfifo_hr
		.phy_read_increment_vfifo_qr (s0_phy_phy_read_increment_vfifo_qr),          //                    .phy_read_increment_vfifo_qr
		.phy_reset_mem_stable        (s0_phy_phy_reset_mem_stable),                 //                    .phy_reset_mem_stable
		.phy_cal_success             (s0_phy_phy_cal_success),                      //                    .phy_cal_success
		.phy_cal_fail                (s0_phy_phy_cal_fail),                         //                    .phy_cal_fail
		.phy_cal_debug_info          (s0_phy_phy_cal_debug_info),                   //                    .phy_cal_debug_info
		.phy_read_fifo_reset         (s0_phy_phy_read_fifo_reset),                  //                    .phy_read_fifo_reset
		.phy_vfifo_rd_en_override    (s0_phy_phy_vfifo_rd_en_override),             //                    .phy_vfifo_rd_en_override
		.phy_read_fifo_q             (p0_phy_phy_read_fifo_q),                      //                    .phy_read_fifo_q
		.calib_skip_steps            (p0_calib_calib_skip_steps),                   //               calib.calib_skip_steps
		.scc_data                    (s0_scc_scc_data),                             //                 scc.scc_data
		.scc_dqs_ena                 (s0_scc_scc_dqs_ena),                          //                    .scc_dqs_ena
		.scc_dqs_io_ena              (s0_scc_scc_dqs_io_ena),                       //                    .scc_dqs_io_ena
		.scc_dq_ena                  (s0_scc_scc_dq_ena),                           //                    .scc_dq_ena
		.scc_dm_ena                  (s0_scc_scc_dm_ena),                           //                    .scc_dm_ena
		.capture_strobe_tracking     (p0_scc_capture_strobe_tracking),              //                    .capture_strobe_tracking
		.scc_upd                     (s0_scc_scc_upd),                              //                    .scc_upd
		.afi_mem_clk_disable         (c0_afi_afi_mem_clk_disable),                  // afi_mem_clk_disable.afi_mem_clk_disable
		.pll_mem_clk                 (pll_mem_clk),                                 //         pll_sharing.pll_mem_clk
		.pll_write_clk               (pll_write_clk),                               //                    .pll_write_clk
		.pll_write_clk_pre_phy_clk   (pll_write_clk_pre_phy_clk),                   //                    .pll_write_clk_pre_phy_clk
		.pll_addr_cmd_clk            (pll_addr_cmd_clk),                            //                    .pll_addr_cmd_clk
		.pll_locked                  (pll_locked),                                  //                    .pll_locked
		.pll_avl_clk                 (pll_avl_clk),                                 //                    .pll_avl_clk
		.pll_config_clk              (pll_config_clk),                              //                    .pll_config_clk
		.pll_mem_phy_clk             (pll_mem_phy_clk),                             //                    .pll_mem_phy_clk
		.afi_phy_clk                 (afi_phy_clk),                                 //                    .afi_phy_clk
		.pll_avl_phy_clk             (pll_avl_phy_clk),                             //                    .pll_avl_phy_clk
		.dll_pll_locked              (p0_dll_sharing_dll_pll_locked),               //         dll_sharing.dll_pll_locked
		.dll_delayctrl               (dll0_dll_sharing_dll_delayctrl),              //                    .dll_delayctrl
		.seriesterminationcontrol    (oct0_oct_sharing_seriesterminationcontrol),   //         oct_sharing.seriesterminationcontrol
		.parallelterminationcontrol  (oct0_oct_sharing_parallelterminationcontrol), //                    .parallelterminationcontrol
		.mem_ca                      (mem_ca),                                      //              memory.mem_ca
		.mem_ck                      (mem_ck),                                      //                    .mem_ck
		.mem_ck_n                    (mem_ck_n),                                    //                    .mem_ck_n
		.mem_cke                     (mem_cke),                                     //                    .mem_cke
		.mem_cs_n                    (mem_cs_n),                                    //                    .mem_cs_n
		.mem_dm                      (mem_dm),                                      //                    .mem_dm
		.mem_dq                      (mem_dq),                                      //                    .mem_dq
		.mem_dqs                     (mem_dqs),                                     //                    .mem_dqs
		.mem_dqs_n                   (mem_dqs_n)                                    //                    .mem_dqs_n
	);

	afi_mux_lpddr2 #(
		.AFI_RATE_RATIO      (2),
		.AFI_ADDR_WIDTH      (40),
		.AFI_BANKADDR_WIDTH  (0),
		.AFI_CONTROL_WIDTH   (4),
		.AFI_CS_WIDTH        (2),
		.AFI_DM_WIDTH        (16),
		.AFI_DQ_WIDTH        (128),
		.AFI_WRITE_DQS_WIDTH (8),
		.AFI_RLAT_WIDTH      (6),
		.AFI_WLAT_WIDTH      (6)
	) m0 (
		.clk                   (afi_clk),                      //     clk.clk
		.afi_addr              (c0_afi_afi_addr),              //     afi.afi_addr
		.afi_cke               (c0_afi_afi_cke),               //        .afi_cke
		.afi_cs_n              (c0_afi_afi_cs_n),              //        .afi_cs_n
		.afi_dqs_burst         (c0_afi_afi_dqs_burst),         //        .afi_dqs_burst
		.afi_wdata_valid       (c0_afi_afi_wdata_valid),       //        .afi_wdata_valid
		.afi_wdata             (c0_afi_afi_wdata),             //        .afi_wdata
		.afi_dm                (c0_afi_afi_dm),                //        .afi_dm
		.afi_rdata             (m0_afi_afi_rdata),             //        .afi_rdata
		.afi_rdata_en          (c0_afi_afi_rdata_en),          //        .afi_rdata_en
		.afi_rdata_en_full     (c0_afi_afi_rdata_en_full),     //        .afi_rdata_en_full
		.afi_rdata_valid       (m0_afi_afi_rdata_valid),       //        .afi_rdata_valid
		.afi_cal_success       (m0_afi_afi_cal_success),       //        .afi_cal_success
		.afi_cal_fail          (m0_afi_afi_cal_fail),          //        .afi_cal_fail
		.afi_wlat              (m0_afi_afi_wlat),              //        .afi_wlat
		.afi_rlat              (m0_afi_afi_rlat),              //        .afi_rlat
		.seq_mux_addr          (s0_afi_afi_addr),              // seq_mux.afi_addr
		.seq_mux_cke           (s0_afi_afi_cke),               //        .afi_cke
		.seq_mux_cs_n          (s0_afi_afi_cs_n),              //        .afi_cs_n
		.seq_mux_dqs_burst     (s0_afi_afi_dqs_burst),         //        .afi_dqs_burst
		.seq_mux_wdata_valid   (s0_afi_afi_wdata_valid),       //        .afi_wdata_valid
		.seq_mux_wdata         (s0_afi_afi_wdata),             //        .afi_wdata
		.seq_mux_dm            (s0_afi_afi_dm),                //        .afi_dm
		.seq_mux_rdata         (m0_seq_mux_afi_rdata),         //        .afi_rdata
		.seq_mux_rdata_en      (s0_afi_afi_rdata_en),          //        .afi_rdata_en
		.seq_mux_rdata_en_full (s0_afi_afi_rdata_en_full),     //        .afi_rdata_en_full
		.seq_mux_rdata_valid   (m0_seq_mux_afi_rdata_valid),   //        .afi_rdata_valid
		.phy_mux_addr          (m0_phy_mux_afi_addr),          // phy_mux.afi_addr
		.phy_mux_cke           (m0_phy_mux_afi_cke),           //        .afi_cke
		.phy_mux_cs_n          (m0_phy_mux_afi_cs_n),          //        .afi_cs_n
		.phy_mux_dqs_burst     (m0_phy_mux_afi_dqs_burst),     //        .afi_dqs_burst
		.phy_mux_wdata_valid   (m0_phy_mux_afi_wdata_valid),   //        .afi_wdata_valid
		.phy_mux_wdata         (m0_phy_mux_afi_wdata),         //        .afi_wdata
		.phy_mux_dm            (m0_phy_mux_afi_dm),            //        .afi_dm
		.phy_mux_rdata         (p0_afi_afi_rdata),             //        .afi_rdata
		.phy_mux_rdata_en      (m0_phy_mux_afi_rdata_en),      //        .afi_rdata_en
		.phy_mux_rdata_en_full (m0_phy_mux_afi_rdata_en_full), //        .afi_rdata_en_full
		.phy_mux_rdata_valid   (p0_afi_afi_rdata_valid),       //        .afi_rdata_valid
		.phy_mux_cal_success   (p0_afi_afi_cal_success),       //        .afi_cal_success
		.phy_mux_cal_fail      (p0_afi_afi_cal_fail),          //        .afi_cal_fail
		.phy_mux_wlat          (p0_afi_afi_wlat),              //        .afi_wlat
		.phy_mux_rlat          (p0_afi_afi_rlat),              //        .afi_rlat
		.mux_sel               (s0_mux_sel_mux_sel)            // mux_sel.mux_sel
	);

	TR4_QSYS_mem_if_lpddr2_emif_s0 s0 (
		.avl_clk                     (p0_avl_clk_clk),                                            //          avl_clk.clk
		.avl_reset_n                 (p0_avl_reset_reset),                                        //        avl_reset.reset_n
		.scc_clk                     (p0_scc_clk_clk),                                            //          scc_clk.clk
		.reset_n_scc_clk             (p0_scc_reset_reset),                                        //        scc_reset.reset_n
		.scc_data                    (s0_scc_scc_data),                                           //              scc.scc_data
		.scc_dqs_ena                 (s0_scc_scc_dqs_ena),                                        //                 .scc_dqs_ena
		.scc_dqs_io_ena              (s0_scc_scc_dqs_io_ena),                                     //                 .scc_dqs_io_ena
		.scc_dq_ena                  (s0_scc_scc_dq_ena),                                         //                 .scc_dq_ena
		.scc_dm_ena                  (s0_scc_scc_dm_ena),                                         //                 .scc_dm_ena
		.capture_strobe_tracking     (p0_scc_capture_strobe_tracking),                            //                 .capture_strobe_tracking
		.scc_upd                     (s0_scc_scc_upd),                                            //                 .scc_upd
		.afi_init_req                (c0_afi_afi_init_req),                                       // afi_init_cal_req.afi_init_req
		.afi_cal_req                 (c0_afi_afi_cal_req),                                        //                 .afi_cal_req
		.seq_waitrequest             (s0_seq_debug_translator_avalon_anti_slave_0_waitrequest),   //        seq_debug.waitrequest
		.seq_readdata                (s0_seq_debug_translator_avalon_anti_slave_0_readdata),      //                 .readdata
		.seq_readdatavalid           (s0_seq_debug_translator_avalon_anti_slave_0_readdatavalid), //                 .readdatavalid
		.seq_burstcount              (s0_seq_debug_translator_avalon_anti_slave_0_burstcount),    //                 .burstcount
		.seq_writedata               (s0_seq_debug_translator_avalon_anti_slave_0_writedata),     //                 .writedata
		.seq_address                 (s0_seq_debug_translator_avalon_anti_slave_0_address),       //                 .address
		.seq_write                   (s0_seq_debug_translator_avalon_anti_slave_0_write),         //                 .write
		.seq_read                    (s0_seq_debug_translator_avalon_anti_slave_0_read),          //                 .read
		.seq_byteenable              (s0_seq_debug_translator_avalon_anti_slave_0_byteenable),    //                 .byteenable
		.phy_clk                     (p0_phy_phy_clk),                                            //              phy.phy_clk
		.phy_reset_n                 (p0_phy_phy_reset_n),                                        //                 .phy_reset_n
		.phy_read_latency_counter    (s0_phy_phy_read_latency_counter),                           //                 .phy_read_latency_counter
		.phy_afi_wlat                (s0_phy_phy_afi_wlat),                                       //                 .phy_afi_wlat
		.phy_afi_rlat                (s0_phy_phy_afi_rlat),                                       //                 .phy_afi_rlat
		.phy_read_increment_vfifo_fr (s0_phy_phy_read_increment_vfifo_fr),                        //                 .phy_read_increment_vfifo_fr
		.phy_read_increment_vfifo_hr (s0_phy_phy_read_increment_vfifo_hr),                        //                 .phy_read_increment_vfifo_hr
		.phy_read_increment_vfifo_qr (s0_phy_phy_read_increment_vfifo_qr),                        //                 .phy_read_increment_vfifo_qr
		.phy_reset_mem_stable        (s0_phy_phy_reset_mem_stable),                               //                 .phy_reset_mem_stable
		.phy_cal_success             (s0_phy_phy_cal_success),                                    //                 .phy_cal_success
		.phy_cal_fail                (s0_phy_phy_cal_fail),                                       //                 .phy_cal_fail
		.phy_cal_debug_info          (s0_phy_phy_cal_debug_info),                                 //                 .phy_cal_debug_info
		.phy_read_fifo_reset         (s0_phy_phy_read_fifo_reset),                                //                 .phy_read_fifo_reset
		.phy_vfifo_rd_en_override    (s0_phy_phy_vfifo_rd_en_override),                           //                 .phy_vfifo_rd_en_override
		.phy_read_fifo_q             (p0_phy_phy_read_fifo_q),                                    //                 .phy_read_fifo_q
		.calib_skip_steps            (p0_calib_calib_skip_steps),                                 //            calib.calib_skip_steps
		.phy_mux_sel                 (s0_mux_sel_mux_sel),                                        //          mux_sel.mux_sel
		.afi_clk                     (afi_clk),                                                   //          afi_clk.clk
		.afi_reset_n                 (afi_reset_n),                                               //        afi_reset.reset_n
		.afi_addr                    (s0_afi_afi_addr),                                           //              afi.afi_addr
		.afi_cke                     (s0_afi_afi_cke),                                            //                 .afi_cke
		.afi_cs_n                    (s0_afi_afi_cs_n),                                           //                 .afi_cs_n
		.afi_dqs_burst               (s0_afi_afi_dqs_burst),                                      //                 .afi_dqs_burst
		.afi_wdata_valid             (s0_afi_afi_wdata_valid),                                    //                 .afi_wdata_valid
		.afi_wdata                   (s0_afi_afi_wdata),                                          //                 .afi_wdata
		.afi_dm                      (s0_afi_afi_dm),                                             //                 .afi_dm
		.afi_rdata                   (m0_seq_mux_afi_rdata),                                      //                 .afi_rdata
		.afi_rdata_en                (s0_afi_afi_rdata_en),                                       //                 .afi_rdata_en
		.afi_rdata_en_full           (s0_afi_afi_rdata_en_full),                                  //                 .afi_rdata_en_full
		.afi_rdata_valid             (m0_seq_mux_afi_rdata_valid),                                //                 .afi_rdata_valid
		.afi_seq_busy                (s0_tracking_afi_seq_busy),                                  //         tracking.afi_seq_busy
		.afi_ctl_refresh_done        (c0_afi_afi_ctl_refresh_done),                               //                 .afi_ctl_refresh_done
		.afi_ctl_long_idle           (c0_afi_afi_ctl_long_idle),                                  //                 .afi_ctl_long_idle
		.seq_debugaccess             (1'b0),                                                      //      (terminated)
		.phy_write_fr_cycle_shifts   ()                                                           //      (terminated)
	);

	TR4_QSYS_mem_if_lpddr2_emif_dmaster #(
		.USE_PLI     (0),
		.PLI_PORT    (50000),
		.FIFO_DEPTHS (2)
	) dmaster (
		.clk_clk              (p0_avl_clk_clk),               //          clk.clk
		.clk_reset_reset      (~p0_avl_reset_reset),          //    clk_reset.reset
		.master_address       (dmaster_master_address),       //       master.address
		.master_readdata      (dmaster_master_readdata),      //             .readdata
		.master_read          (dmaster_master_read),          //             .read
		.master_write         (dmaster_master_write),         //             .write
		.master_writedata     (dmaster_master_writedata),     //             .writedata
		.master_waitrequest   (dmaster_master_waitrequest),   //             .waitrequest
		.master_readdatavalid (dmaster_master_readdatavalid), //             .readdatavalid
		.master_byteenable    (dmaster_master_byteenable),    //             .byteenable
		.master_reset_reset   (dmaster_master_reset_reset)    // master_reset.reset
	);

	TR4_QSYS_mem_if_lpddr2_emif_c0 c0 (
		.afi_reset_n          (afi_reset_n),                 //    afi_reset.reset_n
		.afi_clk              (afi_clk),                     //      afi_clk.clk
		.afi_half_clk         (afi_half_clk),                // afi_half_clk.clk
		.local_init_done      (local_init_done),             //       status.local_init_done
		.local_cal_success    (local_cal_success),           //             .local_cal_success
		.local_cal_fail       (local_cal_fail),              //             .local_cal_fail
		.afi_addr             (c0_afi_afi_addr),             //          afi.afi_addr
		.afi_cke              (c0_afi_afi_cke),              //             .afi_cke
		.afi_cs_n             (c0_afi_afi_cs_n),             //             .afi_cs_n
		.afi_dqs_burst        (c0_afi_afi_dqs_burst),        //             .afi_dqs_burst
		.afi_wdata_valid      (c0_afi_afi_wdata_valid),      //             .afi_wdata_valid
		.afi_wdata            (c0_afi_afi_wdata),            //             .afi_wdata
		.afi_dm               (c0_afi_afi_dm),               //             .afi_dm
		.afi_rdata            (m0_afi_afi_rdata),            //             .afi_rdata
		.afi_rdata_en         (c0_afi_afi_rdata_en),         //             .afi_rdata_en
		.afi_rdata_en_full    (c0_afi_afi_rdata_en_full),    //             .afi_rdata_en_full
		.afi_rdata_valid      (m0_afi_afi_rdata_valid),      //             .afi_rdata_valid
		.afi_mem_clk_disable  (c0_afi_afi_mem_clk_disable),  //             .afi_mem_clk_disable
		.afi_init_req         (c0_afi_afi_init_req),         //             .afi_init_req
		.afi_cal_req          (c0_afi_afi_cal_req),          //             .afi_cal_req
		.afi_seq_busy         (s0_tracking_afi_seq_busy),    //             .afi_seq_busy
		.afi_ctl_refresh_done (c0_afi_afi_ctl_refresh_done), //             .afi_ctl_refresh_done
		.afi_ctl_long_idle    (c0_afi_afi_ctl_long_idle),    //             .afi_ctl_long_idle
		.afi_cal_success      (m0_afi_afi_cal_success),      //             .afi_cal_success
		.afi_cal_fail         (m0_afi_afi_cal_fail),         //             .afi_cal_fail
		.afi_wlat             (m0_afi_afi_wlat),             //             .afi_wlat
		.afi_rlat             (m0_afi_afi_rlat),             //             .afi_rlat
		.avl_ready            (avl_ready),                   //          avl.waitrequest_n
		.avl_burstbegin       (avl_burstbegin),              //             .beginbursttransfer
		.avl_addr             (avl_addr),                    //             .address
		.avl_rdata_valid      (avl_rdata_valid),             //             .readdatavalid
		.avl_rdata            (avl_rdata),                   //             .readdata
		.avl_wdata            (avl_wdata),                   //             .writedata
		.avl_be               (avl_be),                      //             .byteenable
		.avl_read_req         (avl_read_req),                //             .read
		.avl_write_req        (avl_write_req),               //             .write
		.avl_size             (avl_size)                     //             .burstcount
	);

	altera_mem_if_oct_cyclonev #(
		.OCT_TERM_CONTROL_WIDTH (16)
	) oct0 (
		.oct_rzqin                  (oct_rzqin),                                   //         oct.rzqin
		.seriesterminationcontrol   (oct0_oct_sharing_seriesterminationcontrol),   // oct_sharing.seriesterminationcontrol
		.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol)  //            .parallelterminationcontrol
	);

	altera_mem_if_dll_cyclonev #(
		.DLL_DELAY_CTRL_WIDTH       (7),
		.DLL_OFFSET_CTRL_WIDTH      (6),
		.DELAY_BUFFER_MODE          ("HIGH"),
		.DELAY_CHAIN_LENGTH         (8),
		.DLL_INPUT_FREQUENCY_PS_STR ("3333 ps")
	) dll0 (
		.clk            (p0_dll_clk_clk),                 //         clk.clk
		.dll_pll_locked (p0_dll_sharing_dll_pll_locked),  // dll_sharing.dll_pll_locked
		.dll_delayctrl  (dll0_dll_sharing_dll_delayctrl)  //            .dll_delayctrl
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) dmaster_master_translator (
		.clk                      (p0_avl_clk_clk),                                                    //                       clk.clk
		.reset                    (~p0_avl_reset_reset),                                               //                     reset.reset
		.uav_address              (dmaster_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount           (dmaster_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read                 (dmaster_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write                (dmaster_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest          (dmaster_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid        (dmaster_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable           (dmaster_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata             (dmaster_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata            (dmaster_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock                 (dmaster_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess          (dmaster_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address               (dmaster_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest           (dmaster_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable            (dmaster_master_byteenable),                                         //                          .byteenable
		.av_read                  (dmaster_master_read),                                               //                          .read
		.av_readdata              (dmaster_master_readdata),                                           //                          .readdata
		.av_readdatavalid         (dmaster_master_readdatavalid),                                      //                          .readdatavalid
		.av_write                 (dmaster_master_write),                                              //                          .write
		.av_writedata             (dmaster_master_writedata),                                          //                          .writedata
		.av_burstcount            (1'b1),                                                              //               (terminated)
		.av_beginbursttransfer    (1'b0),                                                              //               (terminated)
		.av_begintransfer         (1'b0),                                                              //               (terminated)
		.av_chipselect            (1'b0),                                                              //               (terminated)
		.av_lock                  (1'b0),                                                              //               (terminated)
		.av_debugaccess           (1'b0),                                                              //               (terminated)
		.uav_clken                (),                                                                  //               (terminated)
		.av_clken                 (1'b1),                                                              //               (terminated)
		.uav_response             (2'b00),                                                             //               (terminated)
		.av_response              (),                                                                  //               (terminated)
		.uav_writeresponserequest (),                                                                  //               (terminated)
		.uav_writeresponsevalid   (1'b0),                                                              //               (terminated)
		.av_writeresponserequest  (1'b0),                                                              //               (terminated)
		.av_writeresponsevalid    ()                                                                   //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (32),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) s0_seq_debug_translator (
		.clk                      (p0_avl_clk_clk),                                                    //                      clk.clk
		.reset                    (~p0_avl_reset_reset),                                               //                    reset.reset
		.uav_address              (dmaster_master_translator_avalon_universal_master_0_address),       // avalon_universal_slave_0.address
		.uav_burstcount           (dmaster_master_translator_avalon_universal_master_0_burstcount),    //                         .burstcount
		.uav_read                 (dmaster_master_translator_avalon_universal_master_0_read),          //                         .read
		.uav_write                (dmaster_master_translator_avalon_universal_master_0_write),         //                         .write
		.uav_waitrequest          (dmaster_master_translator_avalon_universal_master_0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid        (dmaster_master_translator_avalon_universal_master_0_readdatavalid), //                         .readdatavalid
		.uav_byteenable           (dmaster_master_translator_avalon_universal_master_0_byteenable),    //                         .byteenable
		.uav_readdata             (dmaster_master_translator_avalon_universal_master_0_readdata),      //                         .readdata
		.uav_writedata            (dmaster_master_translator_avalon_universal_master_0_writedata),     //                         .writedata
		.uav_lock                 (dmaster_master_translator_avalon_universal_master_0_lock),          //                         .lock
		.uav_debugaccess          (dmaster_master_translator_avalon_universal_master_0_debugaccess),   //                         .debugaccess
		.av_address               (s0_seq_debug_translator_avalon_anti_slave_0_address),               //      avalon_anti_slave_0.address
		.av_write                 (s0_seq_debug_translator_avalon_anti_slave_0_write),                 //                         .write
		.av_read                  (s0_seq_debug_translator_avalon_anti_slave_0_read),                  //                         .read
		.av_readdata              (s0_seq_debug_translator_avalon_anti_slave_0_readdata),              //                         .readdata
		.av_writedata             (s0_seq_debug_translator_avalon_anti_slave_0_writedata),             //                         .writedata
		.av_burstcount            (s0_seq_debug_translator_avalon_anti_slave_0_burstcount),            //                         .burstcount
		.av_byteenable            (s0_seq_debug_translator_avalon_anti_slave_0_byteenable),            //                         .byteenable
		.av_readdatavalid         (s0_seq_debug_translator_avalon_anti_slave_0_readdatavalid),         //                         .readdatavalid
		.av_waitrequest           (s0_seq_debug_translator_avalon_anti_slave_0_waitrequest),           //                         .waitrequest
		.av_begintransfer         (),                                                                  //              (terminated)
		.av_beginbursttransfer    (),                                                                  //              (terminated)
		.av_writebyteenable       (),                                                                  //              (terminated)
		.av_lock                  (),                                                                  //              (terminated)
		.av_chipselect            (),                                                                  //              (terminated)
		.av_clken                 (),                                                                  //              (terminated)
		.uav_clken                (1'b0),                                                              //              (terminated)
		.av_debugaccess           (),                                                                  //              (terminated)
		.av_outputenable          (),                                                                  //              (terminated)
		.uav_response             (),                                                                  //              (terminated)
		.av_response              (2'b00),                                                             //              (terminated)
		.uav_writeresponserequest (1'b0),                                                              //              (terminated)
		.uav_writeresponsevalid   (),                                                                  //              (terminated)
		.av_writeresponserequest  (),                                                                  //              (terminated)
		.av_writeresponsevalid    (1'b0)                                                               //              (terminated)
	);

endmodule
