<?xml version="1.0" encoding="UTF-8"?>
<preferences>
 <debug showDebugMenu="0" />
 <systemtable filter="Default">
  <columns>
   <connections preferredWidth="255" />
   <irq preferredWidth="34" />
   <inputclock preferredWidth="209" />
   <description preferredWidth="95" />
   <export preferredWidth="198" />
  </columns>
 </systemtable>
 <clocktable>
  <columns>
   <clockname preferredWidth="244" />
   <clocksource preferredWidth="244" />
   <frequency preferredWidth="225" />
  </columns>
 </clocktable>
 <library
   expandedCategories="Library/Peripherals,Library/Peripherals/Microcontroller Peripherals,Project,Library" />
 <window width="1195" height="884" x="31" y="43" />
 <hdlexample language="VERILOG" />
</preferences>
