--dffpipe DELAY=2 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 9.1SP2 cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.



--synthesis_resources = reg 20 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_pe9
( 
	clock	:	input;
	clrn	:	input;
	d[9..0]	:	input;
	q[9..0]	:	output;
) 
VARIABLE 
	dffe17a[9..0] : dffe;
	dffe18a[9..0] : dffe;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe17a[].clk = clock;
	dffe17a[].clrn = clrn;
	dffe17a[].d = (d[] & (! sclr));
	dffe17a[].ena = ena;
	dffe17a[].prn = prn;
	dffe18a[].clk = clock;
	dffe18a[].clrn = clrn;
	dffe18a[].d = (dffe17a[].q & (! sclr));
	dffe18a[].ena = ena;
	dffe18a[].prn = prn;
	ena = VCC;
	prn = VCC;
	q[] = dffe18a[].q;
	sclr = GND;
END;
--VALID FILE
