
//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

module DE_NANO(

	//////////// CLOCK //////////
	CLOCK_50,

	//////////// LED //////////
	LED,

	//////////// KEY //////////
	KEY,

	//////////// SW //////////
	SW,

	//////////// SDRAM //////////
	DRAM_ADDR,
	DRAM_BA,
	DRAM_CAS_N,
	DRAM_CKE,
	DRAM_CLK,
	DRAM_CS_N,
	DRAM_DQ,
	DRAM_DQM,
	DRAM_RAS_N,
	DRAM_WE_N,

	//////////// Accelerometer and EEPROM //////////
	G_SENSOR_CS_N,
	G_SENSOR_INT,
	I2C_SCLK,
	I2C_SDAT,

	//////////// GPIO_0, GPIO_0 connect to LTM - 4.3" LCD and Touch //////////
	LTM_ADC_BUSY,
	LTM_ADC_DCLK,
	LTM_ADC_DIN,
	LTM_ADC_DOUT,
	LTM_ADC_PENIRQ_n,
	LTM_B,
	LTM_DEN,
	LTM_G,
	LTM_GREST,
	LTM_HD,
	LTM_NCLK,
	LTM_R,
	LTM_SCEN,
	LTM_SDA,
	LTM_VD,

	//////////// GPIO_0, GPIO_1 connect to D5M - 5M Pixel Camera //////////
	D5M_D,
	D5M_FVAL,
	D5M_LVAL,
	D5M_PIXCLK,
	D5M_RESET_N,
	D5M_SCLK,
	D5M_SDATA,
	D5M_STROBE,
	D5M_TRIGGER,
	D5M_XCLKIN 
);

//=======================================================
//  PARAMETER declarations
//=======================================================


//=======================================================
//  PORT declarations
//=======================================================

//////////// CLOCK //////////
input 		          		CLOCK_50;

//////////// LED //////////
output		     [7:0]		LED;

//////////// KEY //////////
input 		     [1:0]		KEY;

//////////// SW //////////
input 		     [3:0]		SW;

//////////// SDRAM //////////
output		    [12:0]		DRAM_ADDR;
output		     [1:0]		DRAM_BA;
output		          		DRAM_CAS_N;
output		          		DRAM_CKE;
output		          		DRAM_CLK;
output		          		DRAM_CS_N;
inout 		    [15:0]		DRAM_DQ;
output		     [1:0]		DRAM_DQM;
output		          		DRAM_RAS_N;
output		          		DRAM_WE_N;

//////////// Accelerometer and EEPROM //////////
output		          		G_SENSOR_CS_N;
input 		          		G_SENSOR_INT;
output		          		I2C_SCLK;
inout 		          		I2C_SDAT;

//////////// GPIO_0, GPIO_0 connect to LTM - 4.3" LCD and Touch //////////
input 		          		LTM_ADC_BUSY;
output		          		LTM_ADC_DCLK;
output		          		LTM_ADC_DIN;
input 		          		LTM_ADC_DOUT;
input 		          		LTM_ADC_PENIRQ_n;
output		     [7:0]		LTM_B;
output		          		LTM_DEN;
output		     [7:0]		LTM_G;
output		          		LTM_GREST;
output		          		LTM_HD;
output		          		LTM_NCLK;
output		     [7:0]		LTM_R;
output		          		LTM_SCEN;
inout 		          		LTM_SDA;
output		          		LTM_VD;

//////////// GPIO_0, GPIO_1 connect to D5M - 5M Pixel Camera //////////
input 		    [11:0]		D5M_D;
input 		          		D5M_FVAL;
input 		          		D5M_LVAL;
input 		          		D5M_PIXCLK;
output		          		D5M_RESET_N;
output		          		D5M_SCLK;
inout 		          		D5M_SDATA;
input 		          		D5M_STROBE;
output		          		D5M_TRIGGER;
output		          		D5M_XCLKIN;


//=======================================================
//  REG/WIRE declarations
//=======================================================
wire	[15:0]	X_Cont;
wire	[15:0]	Y_Cont;
wire	[31:0]	Frame_Cont;

reg		[11:0]	rCCD_DATA;
reg				rCCD_LVAL;
reg				rCCD_FVAL;
wire	[11:0]	mCCD_DATA;
wire			mCCD_DVAL;
wire			mCCD_DVAL_d;
wire	[11:0]	sCCD_R;
wire	[11:0]	sCCD_G;
wire	[11:0]	sCCD_B;
wire			sCCD_DVAL;
wire	[15:0]	Read_DATA1;
wire	[15:0]	Read_DATA2;
wire			Read;

wire			sdram_ctrl_clk;
wire			d5m_clk;
wire			ltm_clk;
wire			ltm_clk_n;

wire			DLY_RST_0;
wire			DLY_RST_1;
wire			DLY_RST_2;
wire			DLY_RST_3;

wire			LTM_CTRL_CLK;

reg				rCCD_PCLK;

//=======================================================
//  Structural coding
//=======================================================
assign	LED[3:0]		=	SW;
assign	LED[7:4]		=	Frame_Cont[5:2];

assign	D5M_XCLKIN		=	d5m_clk;
assign	D5M_RESET_N		=	DLY_RST_1;
assign	D5M_TRIGGER		=	1'b1;

assign	LTM_NCLK		=	ltm_clk_n;
assign	LTM_CTRL_CLK	=	ltm_clk;

assign	LTM_GREST		=	KEY[0];

assign	DRAM_CLK		=	sdram_clk;

always@(posedge sdram_ctrl_clk)
begin
	rCCD_DATA	<=	D5M_D;
	rCCD_LVAL	<=	D5M_LVAL;
	rCCD_FVAL	<=	D5M_FVAL;
	rCCD_PCLK	<=	D5M_PIXCLK;
end

Reset_Delay			u1	(	
							.iCLK(ltm_clk),
							.iRST(KEY[0]),
							.oRST_0(DLY_RST_0),
							.oRST_1(DLY_RST_1),
							.oRST_2(DLY_RST_2),
							.oRST_3(DLY_RST_3)
						);

CCD_Capture			u2	(	
							.oDATA(mCCD_DATA),
							.oDVAL(mCCD_DVAL),
							.oX_Cont(X_Cont),
							.oY_Cont(Y_Cont),
							.oFrame_Cont(Frame_Cont),
							.iDATA(rCCD_DATA),
							.iFVAL(rCCD_FVAL),
							.iLVAL(rCCD_LVAL),
//							.iSTART(!KEY[1]),
							.iSTART(DLY_RST_3),
							.iEND(!SW[0]),
							.iCLK(rCCD_PCLK),
							.iRST(DLY_RST_2)
						);

RAW2RGB				u3	(	
							.iCLK(rCCD_PCLK),
							.iRST_n(DLY_RST_1),
							.iData(mCCD_DATA),
							.iDval(mCCD_DVAL),
							.oRed(sCCD_R),
							.oGreen(sCCD_G),
							.oBlue(sCCD_B),
							.oDval(sCCD_DVAL),
							.iMIRROR(1'b0),
							.iX_Cont(X_Cont),
							.iY_Cont(Y_Cont)
						);

IMG_PLL 			u10	(
							.inclk0(CLOCK_50),
							.c0(d5m_clk),
							.c1(ltm_clk),
							.c2(ltm_clk_n),
							.c3(sdram_ctrl_clk),
							.c4(sdram_clk)
						);

Sdram_Control_4Port	u5	(	
							//	HOST Side						
						    .REF_CLK(CLOCK_50),
						    .RESET_N(1'b1),
							.CLK(sdram_ctrl_clk),

							//	FIFO Write Side 1
							.WR1_DATA({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
							.WR1(sCCD_DVAL),
							.WR1_ADDR(0),
							.WR1_MAX_ADDR(800*480),
							.WR1_LENGTH(9'h100),
							.WR1_LOAD(!DLY_RST_0),
							.WR1_CLK(d5m_clk),

							//	FIFO Write Side 2
							.WR2_DATA(	{1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
							.WR2(sCCD_DVAL),
							.WR2_ADDR(22'h100000),
							.WR2_MAX_ADDR(22'h100000+800*480),
							.WR2_LENGTH(9'h100),
							.WR2_LOAD(!DLY_RST_0),
							.WR2_CLK(d5m_clk),

							//	FIFO Read Side 1
						    .RD1_DATA(Read_DATA1),
				        	.RD1(Read),
				        	.RD1_ADDR(0),
							.RD1_MAX_ADDR(800*480),
							.RD1_LENGTH(9'h100),
							.RD1_LOAD(!DLY_RST_0),
							.RD1_CLK(~LTM_CTRL_CLK),
							
							//	FIFO Read Side 2
						    .RD2_DATA(Read_DATA2),
							.RD2(Read),
							.RD2_ADDR(22'h100000),
							.RD2_MAX_ADDR(22'h100000+800*480),
							.RD2_LENGTH(9'h100),
				        	.RD2_LOAD(!DLY_RST_0),
							.RD2_CLK(~LTM_CTRL_CLK),
							
							//	SDRAM Side
						    .SA(DRAM_ADDR),
						    .BA(DRAM_BA),
        					.CS_N(DRAM_CS_N),
        					.CKE(DRAM_CKE),
        					.RAS_N(DRAM_RAS_N),
        					.CAS_N(DRAM_CAS_N),
        					.WE_N(DRAM_WE_N),
        					.DQ(DRAM_DQ),
        					.DQM(DRAM_DQM)
						);

I2C_CCD_Config 		u6	(	
							//	Host Side
							.iCLK(CLOCK_50),
							.iRST_N(DLY_RST_2),
//							.iEXPOSURE_ADJ(SW[2]),
							.iEXPOSURE_ADJ(KEY[1]),
							.iEXPOSURE_DEC_p(!SW[3]),
							.iMIRROR_SW(1'b0),
							//	I2C Side
							.I2C_SCLK(D5M_SCLK),
							.I2C_SDAT(D5M_SDATA)
						);

touch_tcon			u7	( 	
							.iCLK(LTM_CTRL_CLK),
							.iRST_n(DLY_RST_2),
							// sdram side
							.iREAD_DATA1(Read_DATA1),
							.iREAD_DATA2(Read_DATA2),
							.oREAD_SDRAM_EN(Read),
							// lcd side
							.oLCD_R(LTM_R),
							.oLCD_G(LTM_G),
							.oLCD_B(LTM_B),
							.oHD(LTM_HD),
							.oVD(LTM_VD),
							.oDEN(LTM_DEN)
							);

lcd_3wire_config	u8	(	
							// Host Side
							.iCLK(CLOCK_50),
							.iRST_n(DLY_RST_0),
							// 3 wire Side
							.o3WIRE_SCLK(LTM_ADC_DCLK),
							.io3WIRE_SDAT(LTM_SDA),
							.o3WIRE_SCEN(LTM_SCEN),
							.o3WIRE_BUSY_n()
							);



endmodule
