{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 04 11:15:32 2011 " "Info: Processing started: Tue Jan 04 11:15:32 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE_NANO -c DE_NANO " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE_NANO -c DE_NANO" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/command.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v" { { "Info" "ISGN_ENTITY_NAME" "1 command " "Info: Found entity 1: command" {  } { { "Sdram_Control_4Port/command.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/command.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/control_interface.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_interface " "Info: Found entity 1: control_interface" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/control_interface.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 sdr_data_path.v(68) " "Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/sdr_data_path.v" 68 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdr_data_path.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_data_path " "Info: Found entity 1: sdr_data_path" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/sdr_data_path.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdram_control_4port.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_Control_4Port " "Info: Found entity 1: Sdram_Control_4Port" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdram_fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_FIFO " "Info: Found entity 1: Sdram_FIFO" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/ccd_capture.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file v/ccd_capture.v" { { "Info" "ISGN_ENTITY_NAME" "1 CCD_Capture " "Info: Found entity 1: CCD_Capture" {  } { { "V/CCD_Capture.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/CCD_Capture.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2c_ccd_config.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_CCD_Config " "Info: Found entity 1: I2C_CCD_Config" {  } { { "V/I2C_CCD_Config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_CCD_Config.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2c_controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file v/i2c_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_Controller " "Info: Found entity 1: I2C_Controller" {  } { { "V/I2C_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_Controller.v" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2s_controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file v/i2s_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2S_Controller " "Info: Found entity 1: I2S_Controller" {  } { { "V/I2S_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2S_Controller.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/img_pll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file v/img_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 IMG_PLL " "Info: Found entity 1: IMG_PLL" {  } { { "V/IMG_PLL.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/IMG_PLL.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/lcd_3wire_config.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file v/lcd_3wire_config.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_3wire_config " "Info: Found entity 1: lcd_3wire_config" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/line_buffer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file v/line_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Line_Buffer " "Info: Found entity 1: Line_Buffer" {  } { { "V/Line_Buffer.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/Line_Buffer.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/raw2rgb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file v/raw2rgb.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAW2RGB " "Info: Found entity 1: RAW2RGB" {  } { { "V/RAW2RGB.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/RAW2RGB.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/reset_delay.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file v/reset_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Info: Found entity 1: Reset_Delay" {  } { { "V/Reset_Delay.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/Reset_Delay.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/touch_tcon.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file v/touch_tcon.v" { { "Info" "ISGN_ENTITY_NAME" "1 touch_tcon " "Info: Found entity 1: touch_tcon" {  } { { "V/touch_tcon.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/touch_tcon.v" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "de_nano.v 1 1 " "Warning: Using design file de_nano.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 DE_NANO " "Info: Found entity 1: DE_NANO" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sdram_clk de_nano.v(242) " "Warning (10236): Verilog HDL Implicit Net warning at de_nano.v(242): created implicit net for \"sdram_clk\"" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 242 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "DE_NANO " "Info: Elaborating entity \"DE_NANO\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "G_SENSOR_CS_N de_nano.v(102) " "Warning (10034): Output port \"G_SENSOR_CS_N\" at de_nano.v(102) has no driver" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 102 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "I2C_SCLK de_nano.v(104) " "Warning (10034): Output port \"I2C_SCLK\" at de_nano.v(104) has no driver" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 104 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LTM_ADC_DIN de_nano.v(110) " "Warning (10034): Output port \"LTM_ADC_DIN\" at de_nano.v(110) has no driver" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 110 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:u1 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:u1\"" {  } { { "de_nano.v" "u1" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 204 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CCD_Capture CCD_Capture:u2 " "Info: Elaborating entity \"CCD_Capture\" for hierarchy \"CCD_Capture:u2\"" {  } { { "de_nano.v" "u2" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 220 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ifval_fedge CCD_Capture.v(162) " "Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(162): object \"ifval_fedge\" assigned a value but never read" {  } { { "V/CCD_Capture.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/CCD_Capture.v" 162 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "y_cnt_d CCD_Capture.v(163) " "Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(163): object \"y_cnt_d\" assigned a value but never read" {  } { { "V/CCD_Capture.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/CCD_Capture.v" 163 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CCD_Capture.v(183) " "Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)" {  } { { "V/CCD_Capture.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/CCD_Capture.v" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAW2RGB RAW2RGB:u3 " "Info: Elaborating entity \"RAW2RGB\" for hierarchy \"RAW2RGB:u3\"" {  } { { "de_nano.v" "u3" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 234 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "X_Cont_d2 RAW2RGB.v(78) " "Warning (10036): Verilog HDL or VHDL warning at RAW2RGB.v(78): object \"X_Cont_d2\" assigned a value but never read" {  } { { "V/RAW2RGB.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/RAW2RGB.v" 78 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "Y_Cont_d2 RAW2RGB.v(80) " "Warning (10036): Verilog HDL or VHDL warning at RAW2RGB.v(80): object \"Y_Cont_d2\" assigned a value but never read" {  } { { "V/RAW2RGB.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/RAW2RGB.v" 80 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "mDval RAW2RGB.v(92) " "Warning (10036): Verilog HDL or VHDL warning at RAW2RGB.v(92): object \"mDval\" assigned a value but never read" {  } { { "V/RAW2RGB.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/RAW2RGB.v" 92 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Line_Buffer RAW2RGB:u3\|Line_Buffer:L1 " "Info: Elaborating entity \"Line_Buffer\" for hierarchy \"RAW2RGB:u3\|Line_Buffer:L1\"" {  } { { "V/RAW2RGB.v" "L1" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/RAW2RGB.v" 109 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component " "Info: Elaborating entity \"altshift_taps\" for hierarchy \"RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\"" {  } { { "V/Line_Buffer.v" "altshift_taps_component" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/Line_Buffer.v" 72 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component " "Info: Elaborated megafunction instantiation \"RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\"" {  } { { "V/Line_Buffer.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/Line_Buffer.v" 72 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component " "Info: Instantiated megafunction \"RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altshift_taps " "Info: Parameter \"lpm_type\" = \"altshift_taps\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_taps 3 " "Info: Parameter \"number_of_taps\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "tap_distance 800 " "Info: Parameter \"tap_distance\" = \"800\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 12 " "Info: Parameter \"width\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "V/Line_Buffer.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/Line_Buffer.v" 72 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_inn.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/shift_taps_inn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_inn " "Info: Found entity 1: shift_taps_inn" {  } { { "db/shift_taps_inn.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/shift_taps_inn.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_inn RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\|shift_taps_inn:auto_generated " "Info: Elaborating entity \"shift_taps_inn\" for hierarchy \"RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\|shift_taps_inn:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "c:/altera/91/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_eo81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_eo81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_eo81 " "Info: Found entity 1: altsyncram_eo81" {  } { { "db/altsyncram_eo81.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/altsyncram_eo81.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_eo81 RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\|shift_taps_inn:auto_generated\|altsyncram_eo81:altsyncram2 " "Info: Elaborating entity \"altsyncram_eo81\" for hierarchy \"RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\|shift_taps_inn:auto_generated\|altsyncram_eo81:altsyncram2\"" {  } { { "db/shift_taps_inn.tdf" "altsyncram2" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/shift_taps_inn.tdf" 35 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_auf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_auf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_auf " "Info: Found entity 1: cntr_auf" {  } { { "db/cntr_auf.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/cntr_auf.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_auf RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\|shift_taps_inn:auto_generated\|cntr_auf:cntr1 " "Info: Elaborating entity \"cntr_auf\" for hierarchy \"RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\|shift_taps_inn:auto_generated\|cntr_auf:cntr1\"" {  } { { "db/shift_taps_inn.tdf" "cntr1" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/shift_taps_inn.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_7ic.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_7ic.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_7ic " "Info: Found entity 1: cmpr_7ic" {  } { { "db/cmpr_7ic.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/cmpr_7ic.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_7ic RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\|shift_taps_inn:auto_generated\|cntr_auf:cntr1\|cmpr_7ic:cmpr4 " "Info: Elaborating entity \"cmpr_7ic\" for hierarchy \"RAW2RGB:u3\|Line_Buffer:L1\|altshift_taps:altshift_taps_component\|shift_taps_inn:auto_generated\|cntr_auf:cntr1\|cmpr_7ic:cmpr4\"" {  } { { "db/cntr_auf.tdf" "cmpr4" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/cntr_auf.tdf" 85 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "IMG_PLL IMG_PLL:u10 " "Info: Elaborating entity \"IMG_PLL\" for hierarchy \"IMG_PLL:u10\"" {  } { { "de_nano.v" "u10" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 243 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll IMG_PLL:u10\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"IMG_PLL:u10\|altpll:altpll_component\"" {  } { { "V/IMG_PLL.v" "altpll_component" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/IMG_PLL.v" 106 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "IMG_PLL:u10\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"IMG_PLL:u10\|altpll:altpll_component\"" {  } { { "V/IMG_PLL.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/IMG_PLL.v" 106 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "IMG_PLL:u10\|altpll:altpll_component " "Info: Instantiated megafunction \"IMG_PLL:u10\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Info: Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2 " "Info: Parameter \"clk0_divide_by\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info: Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1 " "Info: Parameter \"clk0_multiply_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Info: Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 2 " "Info: Parameter \"clk1_divide_by\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Info: Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 1 " "Info: Parameter \"clk1_multiply_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Info: Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 2 " "Info: Parameter \"clk2_divide_by\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Info: Parameter \"clk2_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 1 " "Info: Parameter \"clk2_multiply_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 20000 " "Info: Parameter \"clk2_phase_shift\" = \"20000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_divide_by 1 " "Info: Parameter \"clk3_divide_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_duty_cycle 50 " "Info: Parameter \"clk3_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_multiply_by 2 " "Info: Parameter \"clk3_multiply_by\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_phase_shift 0 " "Info: Parameter \"clk3_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_divide_by 1 " "Info: Parameter \"clk4_divide_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_duty_cycle 50 " "Info: Parameter \"clk4_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_multiply_by 2 " "Info: Parameter \"clk4_multiply_by\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_phase_shift -114 " "Info: Parameter \"clk4_phase_shift\" = \"-114\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Info: Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Info: Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Info: Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=IMG_PLL " "Info: Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=IMG_PLL\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info: Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Info: Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Info: Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Info: Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Info: Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Info: Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Info: Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Info: Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Info: Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Info: Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Info: Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Info: Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Info: Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Info: Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Info: Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Info: Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Info: Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Info: Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Info: Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Info: Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Info: Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Info: Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Info: Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Info: Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Info: Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Info: Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Info: Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Info: Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Info: Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Info: Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Info: Parameter \"port_clk2\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_USED " "Info: Parameter \"port_clk3\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_USED " "Info: Parameter \"port_clk4\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Info: Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Info: Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Info: Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Info: Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Info: Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Info: Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Info: Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Info: Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Info: Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Info: Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Info: Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Info: Parameter \"width_clock\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "V/IMG_PLL.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/IMG_PLL.v" 106 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/img_pll_altpll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/img_pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 IMG_PLL_altpll " "Info: Found entity 1: IMG_PLL_altpll" {  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "IMG_PLL_altpll IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated " "Info: Elaborating entity \"IMG_PLL_altpll\" for hierarchy \"IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/91/quartus/libraries/megafunctions/altpll.tdf" 884 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_Control_4Port Sdram_Control_4Port:u5 " "Info: Elaborating entity \"Sdram_Control_4Port\" for hierarchy \"Sdram_Control_4Port:u5\"" {  } { { "de_nano.v" "u5" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 297 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR1_MAX_ADDR Sdram_Control_4Port.v(443) " "Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(443): inferring latch(es) for variable \"rWR1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR2_MAX_ADDR Sdram_Control_4Port.v(443) " "Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(443): inferring latch(es) for variable \"rWR2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD1_MAX_ADDR Sdram_Control_4Port.v(443) " "Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(443): inferring latch(es) for variable \"rRD1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD2_MAX_ADDR Sdram_Control_4Port.v(443) " "Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(443): inferring latch(es) for variable \"rRD2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[0\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[1\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[2\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[3\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[4\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[5\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[6\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[7\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[8\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[9\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[10\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[11\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[12\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[13\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[14\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[15\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[16\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[17\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[18\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[19\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[20\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[21\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[22\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD2_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[0\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[1\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[2\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[3\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[4\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[5\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[6\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[7\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[8\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[9\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[10\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[11\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[12\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[13\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[14\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[15\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[16\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[17\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[18\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[19\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[20\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[21\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[22\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rRD1_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[0\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[1\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[2\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[3\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[4\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[5\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[6\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[7\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[8\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[9\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[10\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[11\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[12\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[13\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[14\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[15\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[16\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[17\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[18\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[19\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[20\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[21\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[22\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR2_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[0\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[1\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[2\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[3\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[4\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[5\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[6\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[7\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[8\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[9\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[10\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[11\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[12\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[13\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[14\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[15\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[16\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[17\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[18\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[19\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[20\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[21\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[22\] Sdram_Control_4Port.v(443) " "Info (10041): Inferred latch for \"rWR1_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(443)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_interface Sdram_Control_4Port:u5\|control_interface:control1 " "Info: Elaborating entity \"control_interface\" for hierarchy \"Sdram_Control_4Port:u5\|control_interface:control1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "control1" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 249 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(162) " "Warning (10230): Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/control_interface.v" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(167) " "Warning (10230): Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/control_interface.v" 167 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "command Sdram_Control_4Port:u5\|command:command1 " "Info: Elaborating entity \"command\" for hierarchy \"Sdram_Control_4Port:u5\|command:command1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "command1" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 275 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe_shift command.v(275) " "Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe_shift\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe1 command.v(275) " "Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe1\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe2 command.v(275) " "Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe2\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdr_data_path Sdram_Control_4Port:u5\|sdr_data_path:data_path1 " "Info: Elaborating entity \"sdr_data_path\" for hierarchy \"Sdram_Control_4Port:u5\|sdr_data_path:data_path1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "data_path1" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 284 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 sdr_data_path.v(68) " "Warning (10230): Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/sdr_data_path.v" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_FIFO Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1 " "Info: Elaborating entity \"Sdram_FIFO\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "write_fifo1" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 297 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Info: Elaborating entity \"dcfifo\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\"" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "dcfifo_component" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Info: Elaborated megafunction instantiation \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\"" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Info: Instantiated megafunction \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Info: Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=M9K " "Info: Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=M9K\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 512 " "Info: Parameter \"lpm_numwords\" = \"512\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Info: Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type dcfifo " "Info: Parameter \"lpm_type\" = \"dcfifo\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Info: Parameter \"lpm_width\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 9 " "Info: Parameter \"lpm_widthu\" = \"9\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Info: Parameter \"overflow_checking\" = \"ON\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdsync_delaypipe 4 " "Info: Parameter \"rdsync_delaypipe\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Info: Parameter \"underflow_checking\" = \"ON\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Info: Parameter \"use_eab\" = \"ON\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "write_aclr_synch OFF " "Info: Parameter \"write_aclr_synch\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrsync_delaypipe 4 " "Info: Parameter \"wrsync_delaypipe\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_seo1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dcfifo_seo1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_seo1 " "Info: Found entity 1: dcfifo_seo1" {  } { { "db/dcfifo_seo1.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 42 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_seo1 Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated " "Info: Elaborating entity \"dcfifo_seo1\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "c:/altera/91/quartus/libraries/megafunctions/dcfifo.tdf" 187 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_gray2bin_6ib.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_6ib.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_gray2bin_6ib " "Info: Found entity 1: a_gray2bin_6ib" {  } { { "db/a_gray2bin_6ib.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/a_gray2bin_6ib.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_gray2bin_6ib Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|a_gray2bin_6ib:rdptr_g_gray2bin " "Info: Elaborating entity \"a_gray2bin_6ib\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|a_gray2bin_6ib:rdptr_g_gray2bin\"" {  } { { "db/dcfifo_seo1.tdf" "rdptr_g_gray2bin" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 57 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_577.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_577.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_577 " "Info: Found entity 1: a_graycounter_577" {  } { { "db/a_graycounter_577.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/a_graycounter_577.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_577 Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|a_graycounter_577:rdptr_g1p " "Info: Elaborating entity \"a_graycounter_577\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|a_graycounter_577:rdptr_g1p\"" {  } { { "db/dcfifo_seo1.tdf" "rdptr_g1p" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 61 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_1lc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_1lc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_1lc " "Info: Found entity 1: a_graycounter_1lc" {  } { { "db/a_graycounter_1lc.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/a_graycounter_1lc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_1lc Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|a_graycounter_1lc:wrptr_g1p " "Info: Elaborating entity \"a_graycounter_1lc\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|a_graycounter_1lc:wrptr_g1p\"" {  } { { "db/dcfifo_seo1.tdf" "wrptr_g1p" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 62 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_0lc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_0lc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_0lc " "Info: Found entity 1: a_graycounter_0lc" {  } { { "db/a_graycounter_0lc.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/a_graycounter_0lc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_0lc Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|a_graycounter_0lc:wrptr_gp " "Info: Elaborating entity \"a_graycounter_0lc\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|a_graycounter_0lc:wrptr_gp\"" {  } { { "db/dcfifo_seo1.tdf" "wrptr_gp" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 63 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rf51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rf51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rf51 " "Info: Found entity 1: altsyncram_rf51" {  } { { "db/altsyncram_rf51.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/altsyncram_rf51.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_rf51 Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram " "Info: Elaborating entity \"altsyncram_rf51\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\"" {  } { { "db/dcfifo_seo1.tdf" "fifo_ram" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 64 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_oe9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_oe9 " "Info: Found entity 1: dffpipe_oe9" {  } { { "db/dffpipe_oe9.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dffpipe_oe9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_oe9 Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:rs_brp " "Info: Elaborating entity \"dffpipe_oe9\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:rs_brp\"" {  } { { "db/dcfifo_seo1.tdf" "rs_brp" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 67 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_sld.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_sld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_sld " "Info: Found entity 1: alt_synch_pipe_sld" {  } { { "db/alt_synch_pipe_sld.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/alt_synch_pipe_sld.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_sld Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|alt_synch_pipe_sld:rs_dgwp " "Info: Elaborating entity \"alt_synch_pipe_sld\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|alt_synch_pipe_sld:rs_dgwp\"" {  } { { "db/dcfifo_seo1.tdf" "rs_dgwp" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 69 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_re9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_re9 " "Info: Found entity 1: dffpipe_re9" {  } { { "db/dffpipe_re9.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dffpipe_re9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_re9 Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|alt_synch_pipe_sld:rs_dgwp\|dffpipe_re9:dffpipe6 " "Info: Elaborating entity \"dffpipe_re9\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|alt_synch_pipe_sld:rs_dgwp\|dffpipe_re9:dffpipe6\"" {  } { { "db/alt_synch_pipe_sld.tdf" "dffpipe6" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/alt_synch_pipe_sld.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_tld.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_tld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_tld " "Info: Found entity 1: alt_synch_pipe_tld" {  } { { "db/alt_synch_pipe_tld.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/alt_synch_pipe_tld.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_tld Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|alt_synch_pipe_tld:ws_dgrp " "Info: Elaborating entity \"alt_synch_pipe_tld\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|alt_synch_pipe_tld:ws_dgrp\"" {  } { { "db/dcfifo_seo1.tdf" "ws_dgrp" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 72 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_se9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_se9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_se9 " "Info: Found entity 1: dffpipe_se9" {  } { { "db/dffpipe_se9.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dffpipe_se9.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_se9 Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|alt_synch_pipe_tld:ws_dgrp\|dffpipe_se9:dffpipe9 " "Info: Elaborating entity \"dffpipe_se9\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|alt_synch_pipe_tld:ws_dgrp\|dffpipe_se9:dffpipe9\"" {  } { { "db/alt_synch_pipe_tld.tdf" "dffpipe9" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/alt_synch_pipe_tld.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_n76.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_n76.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_n76 " "Info: Found entity 1: cmpr_n76" {  } { { "db/cmpr_n76.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/cmpr_n76.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_n76 Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|cmpr_n76:rdempty_eq_comp " "Info: Elaborating entity \"cmpr_n76\" for hierarchy \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|cmpr_n76:rdempty_eq_comp\"" {  } { { "db/dcfifo_seo1.tdf" "rdempty_eq_comp" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 79 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_CCD_Config I2C_CCD_Config:u6 " "Info: Elaborating entity \"I2C_CCD_Config\" for hierarchy \"I2C_CCD_Config:u6\"" {  } { { "de_nano.v" "u6" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 310 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(121) " "Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(121): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_CCD_Config.v" 121 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(122) " "Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(122): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_CCD_Config.v" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(160) " "Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_CCD_Config.v" 160 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_Controller I2C_CCD_Config:u6\|I2C_Controller:u0 " "Info: Elaborating entity \"I2C_Controller\" for hierarchy \"I2C_CCD_Config:u6\|I2C_Controller:u0\"" {  } { { "V/I2C_CCD_Config.v" "u0" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_CCD_Config.v" 202 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(70) " "Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_Controller.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(69) " "Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_Controller.v" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "touch_tcon touch_tcon:u7 " "Info: Elaborating entity \"touch_tcon\" for hierarchy \"touch_tcon:u7\"" {  } { { "de_nano.v" "u7" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 326 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_3wire_config lcd_3wire_config:u8 " "Info: Elaborating entity \"lcd_3wire_config\" for hierarchy \"lcd_3wire_config:u8\"" {  } { { "de_nano.v" "u8" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 337 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g0 lcd_3wire_config.v(82) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(82): object \"g0\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 82 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g1 lcd_3wire_config.v(83) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(83): object \"g1\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 83 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g2 lcd_3wire_config.v(84) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(84): object \"g2\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 84 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g3 lcd_3wire_config.v(85) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(85): object \"g3\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 85 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g4 lcd_3wire_config.v(86) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(86): object \"g4\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 86 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g5 lcd_3wire_config.v(87) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(87): object \"g5\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 87 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g6 lcd_3wire_config.v(88) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(88): object \"g6\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 88 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g7 lcd_3wire_config.v(89) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(89): object \"g7\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 89 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g8 lcd_3wire_config.v(90) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(90): object \"g8\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 90 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g9 lcd_3wire_config.v(91) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(91): object \"g9\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 91 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g10 lcd_3wire_config.v(92) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(92): object \"g10\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 92 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g11 lcd_3wire_config.v(93) " "Warning (10036): Verilog HDL or VHDL warning at lcd_3wire_config.v(93): object \"g11\" assigned a value but never read" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 93 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2S_Controller lcd_3wire_config:u8\|I2S_Controller:u0 " "Info: Elaborating entity \"I2S_Controller\" for hierarchy \"lcd_3wire_config:u8\|I2S_Controller:u0\"" {  } { { "V/lcd_3wire_config.v" "u0" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 114 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Warning: Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Warning: Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[0\] " "Warning (14320): Synthesized away node \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[0\]\"" {  } { { "db/altsyncram_rf51.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/altsyncram_rf51.tdf" 41 2 0 } } { "db/dcfifo_seo1.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 64 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/dcfifo.tdf" 187 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 339 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 297 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[1\] " "Warning (14320): Synthesized away node \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[1\]\"" {  } { { "db/altsyncram_rf51.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/altsyncram_rf51.tdf" 73 2 0 } } { "db/dcfifo_seo1.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 64 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/dcfifo.tdf" 187 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 339 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 297 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[10\] " "Warning (14320): Synthesized away node \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[10\]\"" {  } { { "db/altsyncram_rf51.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/altsyncram_rf51.tdf" 361 2 0 } } { "db/dcfifo_seo1.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 64 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/dcfifo.tdf" 187 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 339 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 297 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[11\] " "Warning (14320): Synthesized away node \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[11\]\"" {  } { { "db/altsyncram_rf51.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/altsyncram_rf51.tdf" 393 2 0 } } { "db/dcfifo_seo1.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 64 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/dcfifo.tdf" 187 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 339 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 297 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[15\] " "Warning (14320): Synthesized away node \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[15\]\"" {  } { { "db/altsyncram_rf51.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/altsyncram_rf51.tdf" 521 2 0 } } { "db/dcfifo_seo1.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 64 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/dcfifo.tdf" 187 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 339 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 297 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[0\] " "Warning (14320): Synthesized away node \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[0\]\"" {  } { { "db/altsyncram_rf51.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/altsyncram_rf51.tdf" 41 2 0 } } { "db/dcfifo_seo1.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 64 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/dcfifo.tdf" 187 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 326 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 297 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[1\] " "Warning (14320): Synthesized away node \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[1\]\"" {  } { { "db/altsyncram_rf51.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/altsyncram_rf51.tdf" 73 2 0 } } { "db/dcfifo_seo1.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 64 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/dcfifo.tdf" 187 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 326 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 297 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[15\] " "Warning (14320): Synthesized away node \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|altsyncram_rf51:fifo_ram\|q_b\[15\]\"" {  } { { "db/altsyncram_rf51.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/altsyncram_rf51.tdf" 521 2 0 } } { "db/dcfifo_seo1.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/dcfifo_seo1.tdf" 64 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/dcfifo.tdf" 187 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_FIFO.v" 99 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 326 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 297 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 -1}  } {  } 0 0 "Synthesized away the following node(s):" 0 0 "" 0 -1}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "6 " "Warning: 6 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 0 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "Warning: The following bidir pins have no drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "I2C_SDAT " "Warning: Bidir \"I2C_SDAT\" has no driver" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 105 -1 0 } }  } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1}  } {  } 0 0 "The following bidir pins have no drivers" 0 0 "" 0 -1}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "V/I2S_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2S_Controller.v" 111 -1 0 } } { "V/I2C_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_Controller.v" 64 -1 0 } } { "V/touch_tcon.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/touch_tcon.v" 93 -1 0 } } { "db/a_graycounter_577.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/a_graycounter_577.tdf" 32 2 0 } } { "V/I2C_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_Controller.v" 59 -1 0 } } { "V/I2C_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_Controller.v" 63 -1 0 } } { "db/a_graycounter_577.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/a_graycounter_577.tdf" 45 2 0 } } { "db/a_graycounter_0lc.tdf" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/a_graycounter_0lc.tdf" 37 2 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 -1}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[12\] GND " "Warning (13410): Pin \"DRAM_ADDR\[12\]\" is stuck at GND" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 90 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CKE VCC " "Warning (13410): Pin \"DRAM_CKE\" is stuck at VCC" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 93 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "G_SENSOR_CS_N GND " "Warning (13410): Pin \"G_SENSOR_CS_N\" is stuck at GND" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 102 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "I2C_SCLK GND " "Warning (13410): Pin \"I2C_SCLK\" is stuck at GND" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 104 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LTM_ADC_DIN GND " "Warning (13410): Pin \"LTM_ADC_DIN\" is stuck at GND" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 110 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "D5M_TRIGGER VCC " "Warning (13410): Pin \"D5M_TRIGGER\" is stuck at VCC" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 133 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Info: Timing-Driven Synthesis is running" {  } {  } 0 0 "Timing-Driven Synthesis is running" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "42 42 " "Info: 42 registers lost all their fanouts during netlist optimizations. The first 42 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|mDATAOUT\[0\] " "Info: Register \"Sdram_Control_4Port:u5\|mDATAOUT\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|mDATAOUT\[1\] " "Info: Register \"Sdram_Control_4Port:u5\|mDATAOUT\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|mDATAOUT\[15\] " "Info: Register \"Sdram_Control_4Port:u5\|mDATAOUT\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:ws_bwp\|dffe15a\[9\] " "Info: Register \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:ws_bwp\|dffe15a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:ws_brp\|dffe15a\[9\] " "Info: Register \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:ws_brp\|dffe15a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:ws_bwp\|dffe15a\[9\] " "Info: Register \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:ws_bwp\|dffe15a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:ws_brp\|dffe15a\[9\] " "Info: Register \"Sdram_Control_4Port:u5\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:ws_brp\|dffe15a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:rs_bwp\|dffe15a\[9\] " "Info: Register \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:rs_bwp\|dffe15a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:rs_brp\|dffe15a\[9\] " "Info: Register \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo2\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:rs_brp\|dffe15a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:rs_bwp\|dffe15a\[9\] " "Info: Register \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:rs_bwp\|dffe15a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:rs_brp\|dffe15a\[9\] " "Info: Register \"Sdram_Control_4Port:u5\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_seo1:auto_generated\|dffpipe_oe9:rs_brp\|dffe15a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd_3wire_config:u8\|msetup_st~9 " "Info: Register \"lcd_3wire_config:u8\|msetup_st~9\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd_3wire_config:u8\|msetup_st~10 " "Info: Register \"lcd_3wire_config:u8\|msetup_st~10\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd_3wire_config:u8\|msetup_st~12 " "Info: Register \"lcd_3wire_config:u8\|msetup_st~12\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "I2C_CCD_Config:u6\|mSetup_ST~9 " "Info: Register \"I2C_CCD_Config:u6\|mSetup_ST~9\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "I2C_CCD_Config:u6\|mSetup_ST~10 " "Info: Register \"I2C_CCD_Config:u6\|mSetup_ST~10\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[6\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[6\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[7\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[8\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[8\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[9\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[10\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[10\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[11\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[11\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[12\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[12\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[13\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[13\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[14\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[14\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[15\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[16\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[17\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[17\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[18\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[18\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[19\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[19\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[20\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[20\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[21\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[21\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[22\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[22\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[23\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[24\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[25\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[26\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[26\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[27\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[27\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[28\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[28\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[29\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[29\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[30\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[30\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "CCD_Capture:u2\|Frame_Cont\[31\] " "Info: Register \"CCD_Capture:u2\|Frame_Cont\[31\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "5 " "Warning: Design contains 5 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "G_SENSOR_INT " "Warning (15610): No output dependent on input pin \"G_SENSOR_INT\"" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 103 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "LTM_ADC_BUSY " "Warning (15610): No output dependent on input pin \"LTM_ADC_BUSY\"" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 108 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "LTM_ADC_DOUT " "Warning (15610): No output dependent on input pin \"LTM_ADC_DOUT\"" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 111 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "LTM_ADC_PENIRQ_n " "Warning (15610): No output dependent on input pin \"LTM_ADC_PENIRQ_n\"" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 112 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "D5M_STROBE " "Warning (15610): No output dependent on input pin \"D5M_STROBE\"" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 132 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2005 " "Info: Implemented 2005 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Info: Implemented 27 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "69 " "Info: Implemented 69 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "19 " "Info: Implemented 19 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "1797 " "Info: Implemented 1797 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "92 " "Info: Implemented 92 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 PLLs" {  } {  } 0 0 "Implemented %1!d! PLLs" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 65 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 65 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "198 " "Info: Peak virtual memory: 198 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 04 11:15:51 2011 " "Info: Processing ended: Tue Jan 04 11:15:51 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Info: Total CPU time (on all processors): 00:00:18" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 04 11:15:52 2011 " "Info: Processing started: Tue Jan 04 11:15:52 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE_NANO -c DE_NANO " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE_NANO -c DE_NANO" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE_NANO EP4CE22F17C6 " "Info: Selected device EP4CE22F17C6 for design \"DE_NANO\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Info: high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Info: low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_PLL_COMPUTATION_SUCCESS_WITH_WARNINGS" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Warning: Implemented PLL \"IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type, but with warnings" { { "Warning" "WCUT_CUT_YGR_PLL_PARAMETER_DIFF2" "phase shift IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[4\] -4.1 degrees -7.5 degrees " "Warning: Can't achieve requested value -4.1 degrees for clock output IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[4\] of parameter phase shift -- achieved value of -7.5 degrees" {  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 43 -1 0 } }  } 0 0 "Can't achieve requested value %3!s! for clock output %2!s! of parameter %1!s! -- achieved value of %4!s!" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] 1 2 0 0 " "Info: Implementing clock multiplication of 1, clock division of 2, and phase shift of 0 degrees (0 ps) for IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] port" {  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 43 -1 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] 1 2 0 0 " "Info: Implementing clock multiplication of 1, clock division of 2, and phase shift of 0 degrees (0 ps) for IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] port" {  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 43 -1 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[2\] 1 2 180 20000 " "Info: Implementing clock multiplication of 1, clock division of 2, and phase shift of 180 degrees (20000 ps) for IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[2\] port" {  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 43 -1 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[3\] 2 1 0 0 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[3\] port" {  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 43 -1 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[4\] 2 1 -7 -208 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of -7 degrees (-208 ps) for IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[4\] port" {  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 43 -1 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 77 -1 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type, but with warnings" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Info: Device EP4CE10F17C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Info: Device EP4CE6F17C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Info: Device EP4CE15F17C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Info: Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Info: Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 5938 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Info: Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 5940 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Info: Pin ~ALTERA_DCLK~ is reserved at location H1" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 5942 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Info: Pin ~ALTERA_DATA0~ is reserved at location H2" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 5944 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Info: Pin ~ALTERA_nCEO~ is reserved at location F16" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 5946 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_seo1 " "Info: Entity dcfifo_seo1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_se9:dffpipe9\|dffe10a*  " "Info: set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_se9:dffpipe9\|dffe10a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_re9:dffpipe6\|dffe7a*  " "Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_re9:dffpipe6\|dffe7a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "DE_NANO.SDC " "Info: Reading SDC File: 'DE_NANO.SDC'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL Clocks " "Info: Deriving PLL Clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -phase 180.00 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -phase 180.00 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -7.50 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -7.50 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Info: Clock uncertainty calculation is delayed until the next update_timing_netlist call" {  } {  } 0 0 "Clock uncertainty calculation is delayed until the next update_timing_netlist call" 0 0 "" 0 -1}
{ "Warning" "WSTA_FILTERS_COULD_NOT_BE_MATCHED" "" "Warning: At least one of the filters had some problems and could not be matched" { { "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED" "clk clock " "Warning: clk could not be matched with a clock" {  } {  } 0 0 "%1!s! could not be matched with a %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "At least one of the filters had some problems and could not be matched" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_input_delay -add_delay -clock \[get_clocks \{clk\}\] 1.500 \[all_inputs\] " "Warning: Ignored assignment: set_input_delay -add_delay -clock \[get_clocks \{clk\}\] 1.500 \[all_inputs\]" { { "Warning" "WSTA_NOT_AN_OBJECT_ID" "-clock " "Warning: Argument -clock is not an object ID" {  } {  } 0 0 "Argument %1!s! is not an object ID" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.557 \[get_ports \{DRAM_DQ*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.557 \[get_ports \{DRAM_DQ*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_DQ*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_DQ*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_ADDR*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_ADDR*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.820 \[get_ports \{DRAM_ADDR*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.820 \[get_ports \{DRAM_ADDR*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_FILTERS_COULD_NOT_BE_MATCHED" "" "Warning: At least one of the filters had some problems and could not be matched" { { "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED" "DRAM_*DQM port " "Warning: DRAM_*DQM could not be matched with a port" {  } {  } 0 0 "%1!s! could not be matched with a %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "At least one of the filters had some problems and could not be matched" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.652 \[get_ports \{DRAM_*DQM\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.652 \[get_ports \{DRAM_*DQM\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Positional argument <targets> \[get_ports \{DRAM_*DQM\}\] " "Warning: Positional argument <targets> with value \[get_ports \{DRAM_*DQM\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1} { "Warning" "WSTA_IO_ASSIGNMENT_ENTIRE_OBJECT_LIST_INVALID_TYPE" "\[get_ports \{DRAM_*DQM\}\] output " "Warning: Positional argument: object_list targets with value \[get_ports \{DRAM_*DQM\}\] contains no output ports" {  } {  } 0 0 "Positional argument: object_list targets with value %1!s! contains no %2!s! ports" 0 0 "" 0 -1} { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.781 \[get_ports \{DRAM_*DQM\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.781 \[get_ports \{DRAM_*DQM\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Positional argument <targets> \[get_ports \{DRAM_*DQM\}\] " "Warning: Positional argument <targets> with value \[get_ports \{DRAM_*DQM\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1} { "Warning" "WSTA_IO_ASSIGNMENT_ENTIRE_OBJECT_LIST_INVALID_TYPE" "\[get_ports \{DRAM_*DQM\}\] output " "Warning: Positional argument: object_list targets with value \[get_ports \{DRAM_*DQM\}\] contains no output ports" {  } {  } 0 0 "Positional argument: object_list targets with value %1!s! contains no %2!s! ports" 0 0 "" 0 -1} { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.494 \[get_ports \{DRAM_BA*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.494 \[get_ports \{DRAM_BA*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.806 \[get_ports \{DRAM_BA*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.806 \[get_ports \{DRAM_BA*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_RAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_RAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.779 \[get_ports \{DRAM_RAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.779 \[get_ports \{DRAM_RAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.513 \[get_ports \{DRAM_CAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.513 \[get_ports \{DRAM_CAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.787 \[get_ports \{DRAM_CAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.787 \[get_ports \{DRAM_CAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.628 \[get_ports \{DRAM_WE_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.628 \[get_ports \{DRAM_WE_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.672 \[get_ports \{DRAM_WE_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.672 \[get_ports \{DRAM_WE_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.492 \[get_ports \{DRAM_CKE\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.492 \[get_ports \{DRAM_CKE\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_CKE\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_CKE\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.544 \[get_ports \{DRAM_CS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.544 \[get_ports \{DRAM_CS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.756 \[get_ports \{DRAM_CS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.756 \[get_ports \{DRAM_CS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rCCD_PCLK " "Warning: Node: rCCD_PCLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_CCD_Config:u6\|mI2C_CTRL_CLK " "Warning: Node: I2C_CCD_Config:u6\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK " "Warning: Node: lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "Info: The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 0 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Info: Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "Info:   Period   Clock Name" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "Info: ======== ============" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "Info:   20.000     CLOCK_50" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " "Info:   40.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "Info:   40.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[2\] " "Info:   40.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  10.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " "Info:   10.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  10.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[4\] " "Info:   10.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Info: Automatically promoted node IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 77 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { IMG_PLL:u10|altpll:altpll_component|IMG_PLL_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 956 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C4 of PLL_4) " "Info: Automatically promoted node IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C4 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 77 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { IMG_PLL:u10|altpll:altpll_component|IMG_PLL_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 956 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C3 of PLL_4) " "Info: Automatically promoted node IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C3 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G16 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G16" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 77 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { IMG_PLL:u10|altpll:altpll_component|IMG_PLL_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 956 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[3\] (placed in counter C1 of PLL_4) " "Info: Automatically promoted node IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[3\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 77 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { IMG_PLL:u10|altpll:altpll_component|IMG_PLL_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 956 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[4\] (placed in counter C2 of PLL_4) " "Info: Automatically promoted node IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|wire_pll1_clk\[4\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 77 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { IMG_PLL:u10|altpll:altpll_component|IMG_PLL_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 956 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rCCD_PCLK  " "Info: Automatically promoted node rCCD_PCLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 170 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { rCCD_PCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1436 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "I2C_CCD_Config:u6\|mI2C_CTRL_CLK  " "Info: Automatically promoted node I2C_CCD_Config:u6\|mI2C_CTRL_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_CCD_Config:u6\|I2C_Controller:u0\|I2C_SCLK~1 " "Info: Destination node I2C_CCD_Config:u6\|I2C_Controller:u0\|I2C_SCLK~1" {  } { { "V/I2C_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_Controller.v" 58 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_CCD_Config:u6|I2C_Controller:u0|I2C_SCLK~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 2099 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_CCD_Config:u6\|mI2C_CTRL_CLK~0 " "Info: Destination node I2C_CCD_Config:u6\|mI2C_CTRL_CLK~0" {  } { { "V/I2C_CCD_Config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_CCD_Config.v" 66 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_CCD_Config:u6|mI2C_CTRL_CLK~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 2219 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "V/I2C_CCD_Config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_CCD_Config.v" 66 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_CCD_Config:u6|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 436 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK  " "Info: Automatically promoted node lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd_3wire_config:u8\|I2S_Controller:u0\|I2S_CLK " "Info: Destination node lcd_3wire_config:u8\|I2S_Controller:u0\|I2S_CLK" {  } { { "V/I2S_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2S_Controller.v" 66 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd_3wire_config:u8|I2S_Controller:u0|I2S_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 140 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK~0 " "Info: Destination node lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK~0" {  } { { "V/I2S_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2S_Controller.v" 89 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd_3wire_config:u8|I2S_Controller:u0|mI2S_CLK~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 2138 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "V/I2S_Controller.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2S_Controller.v" 89 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd_3wire_config:u8|I2S_Controller:u0|mI2S_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 132 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Reset_Delay:u1\|oRST_0  " "Info: Automatically promoted node Reset_Delay:u1\|oRST_0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sdram_Control_4Port:u5\|mWR~3 " "Info: Destination node Sdram_Control_4Port:u5\|mWR~3" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 177 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u5|mWR~3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 2653 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd_3wire_config:u8\|m3wire_data\[0\]~0 " "Info: Destination node lcd_3wire_config:u8\|m3wire_data\[0\]~0" {  } { { "V/lcd_3wire_config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/lcd_3wire_config.v" 127 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd_3wire_config:u8|m3wire_data[0]~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 3194 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sdram_Control_4Port:u5\|rRD1_ADDR\[9\]~17 " "Info: Destination node Sdram_Control_4Port:u5\|rRD1_ADDR\[9\]~17" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 476 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u5|rRD1_ADDR[9]~17 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 3259 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sdram_Control_4Port:u5\|rRD1_ADDR\[9\]~21 " "Info: Destination node Sdram_Control_4Port:u5\|rRD1_ADDR\[9\]~21" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 476 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u5|rRD1_ADDR[9]~21 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 3264 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sdram_Control_4Port:u5\|rWR2_ADDR\[19\]~17 " "Info: Destination node Sdram_Control_4Port:u5\|rWR2_ADDR\[19\]~17" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 476 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u5|rWR2_ADDR[19]~17 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 3267 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sdram_Control_4Port:u5\|rWR2_ADDR\[19\]~19 " "Info: Destination node Sdram_Control_4Port:u5\|rWR2_ADDR\[19\]~19" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 476 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u5|rWR2_ADDR[19]~19 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 3273 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sdram_Control_4Port:u5\|rRD2_ADDR\[13\]~17 " "Info: Destination node Sdram_Control_4Port:u5\|rRD2_ADDR\[13\]~17" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 476 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u5|rRD2_ADDR[13]~17 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 3276 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sdram_Control_4Port:u5\|rRD2_ADDR\[13\]~20 " "Info: Destination node Sdram_Control_4Port:u5\|rRD2_ADDR\[13\]~20" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 476 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u5|rRD2_ADDR[13]~20 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 3282 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sdram_Control_4Port:u5\|rWR1_ADDR\[13\]~17 " "Info: Destination node Sdram_Control_4Port:u5\|rWR1_ADDR\[13\]~17" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 476 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u5|rWR1_ADDR[13]~17 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 3285 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sdram_Control_4Port:u5\|rWR1_ADDR\[13\]~20 " "Info: Destination node Sdram_Control_4Port:u5\|rWR1_ADDR\[13\]~20" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/Sdram_Control_4Port/Sdram_Control_4Port.v" 476 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sdram_Control_4Port:u5|rWR1_ADDR[13]~20 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 3291 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "V/Reset_Delay.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/Reset_Delay.v" 46 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:u1|oRST_0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1326 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Reset_Delay:u1\|oRST_2  " "Info: Automatically promoted node Reset_Delay:u1\|oRST_2 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_CCD_Config:u6\|i2c_reset " "Info: Destination node I2C_CCD_Config:u6\|i2c_reset" {  } { { "V/I2C_CCD_Config.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/I2C_CCD_Config.v" 162 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_CCD_Config:u6|i2c_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 434 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Reset_Delay:u1\|oRST_2~0 " "Info: Destination node Reset_Delay:u1\|oRST_2~0" {  } { { "V/Reset_Delay.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/Reset_Delay.v" 48 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:u1|oRST_2~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 2230 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "V/Reset_Delay.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/Reset_Delay.v" 48 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:u1|oRST_2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1328 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Reset_Delay:u1\|oRST_1  " "Info: Automatically promoted node Reset_Delay:u1\|oRST_1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Reset_Delay:u1\|oRST_1~0 " "Info: Destination node Reset_Delay:u1\|oRST_1~0" {  } { { "V/Reset_Delay.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/Reset_Delay.v" 47 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:u1|oRST_1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 2191 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "D5M_RESET_N~output " "Info: Destination node D5M_RESET_N~output" {  } { { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 129 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_RESET_N~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 5891 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "V/Reset_Delay.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/Reset_Delay.v" 47 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:u1|oRST_1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1327 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|pll1 clk\[0\] D5M_XCLKIN~output " "Warning: PLL \"IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|pll1\" output port clk\[0\] feeds output pin \"D5M_XCLKIN~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/altpll.tdf" 884 3 0 } } { "V/IMG_PLL.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/IMG_PLL.v" 106 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 243 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 134 -1 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|pll1 clk\[2\] LTM_NCLK~output " "Warning: PLL \"IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|pll1\" output port clk\[2\] feeds output pin \"LTM_NCLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/altpll.tdf" 884 3 0 } } { "V/IMG_PLL.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/IMG_PLL.v" 106 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 243 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 118 -1 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|pll1 clk\[4\] DRAM_CLK~output " "Warning: PLL \"IMG_PLL:u10\|altpll:altpll_component\|IMG_PLL_altpll:auto_generated\|pll1\" output port clk\[4\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "db/img_pll_altpll.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/db/img_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/91/quartus/libraries/megafunctions/altpll.tdf" 884 3 0 } } { "V/IMG_PLL.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/V/IMG_PLL.v" 106 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 243 0 0 } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 94 -1 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:07 " "Info: Fitter preparation operations ending: elapsed time is 00:00:07" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:08 " "Info: Fitter placement operations ending: elapsed time is 00:00:08" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "8 X21_Y11 X31_Y22 " "Info: Peak interconnect usage is 8% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:08 " "Info: Fitter routing operations ending: elapsed time is 00:00:08" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "EP4CE22F17C6 " "Warning: Timing characteristics of device EP4CE22F17C6 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "46 " "Warning: 46 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone&nbsp;III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems)." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "G_SENSOR_INT 3.3-V LVTTL M2 " "Info: Pin G_SENSOR_INT uses I/O standard 3.3-V LVTTL at M2" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { G_SENSOR_INT } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 103 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { G_SENSOR_INT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1447 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LTM_ADC_BUSY 3.3-V LVTTL B8 " "Info: Pin LTM_ADC_BUSY uses I/O standard 3.3-V LVTTL at B8" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { LTM_ADC_BUSY } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "LTM_ADC_BUSY" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 108 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { LTM_ADC_BUSY } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1450 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LTM_ADC_DOUT 3.3-V LVTTL D3 " "Info: Pin LTM_ADC_DOUT uses I/O standard 3.3-V LVTTL at D3" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { LTM_ADC_DOUT } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "LTM_ADC_DOUT" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 111 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { LTM_ADC_DOUT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1453 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LTM_ADC_PENIRQ_n 3.3-V LVTTL A8 " "Info: Pin LTM_ADC_PENIRQ_n uses I/O standard 3.3-V LVTTL at A8" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { LTM_ADC_PENIRQ_n } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "LTM_ADC_PENIRQ_n" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 112 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { LTM_ADC_PENIRQ_n } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1454 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_STROBE 3.3-V LVTTL R16 " "Info: Pin D5M_STROBE uses I/O standard 3.3-V LVTTL at R16" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_STROBE } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_STROBE" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 132 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_STROBE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1468 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Info: Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 105 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1449 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL G2 " "Info: Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at G2" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1382 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G1 " "Info: Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G1" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1383 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL L8 " "Info: Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at L8" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1384 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL K5 " "Info: Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at K5" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1385 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL K2 " "Info: Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at K2" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1386 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL J2 " "Info: Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at J2" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1387 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL J1 " "Info: Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at J1" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1388 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL R7 " "Info: Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at R7" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1389 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL T4 " "Info: Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at T4" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1390 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL T2 " "Info: Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at T2" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1391 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL T3 " "Info: Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at T3" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1392 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL R3 " "Info: Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at R3" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1393 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL R5 " "Info: Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at R5" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1394 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL P3 " "Info: Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at P3" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1395 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL N3 " "Info: Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at N3" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1396 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL K1 " "Info: Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at K1" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 96 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1397 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LTM_SDA 3.3-V LVTTL B12 " "Info: Pin LTM_SDA uses I/O standard 3.3-V LVTTL at B12" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { LTM_SDA } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "LTM_SDA" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 121 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { LTM_SDA } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1460 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_SDATA 3.3-V LVTTL P16 " "Info: Pin D5M_SDATA uses I/O standard 3.3-V LVTTL at P16" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_SDATA } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_SDATA" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 131 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_SDATA } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1467 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Info: Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { SW[0] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 87 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1363 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Info: Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { SW[1] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 87 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1364 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Info: Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { SW[2] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 87 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1365 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Info: Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { SW[3] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 87 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1366 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Info: Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { KEY[0] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 84 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1361 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Info: Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 78 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1439 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_PIXCLK 3.3-V LVTTL T9 " "Info: Pin D5M_PIXCLK uses I/O standard 3.3-V LVTTL at T9" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_PIXCLK } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_PIXCLK" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 128 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_PIXCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1464 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_FVAL 3.3-V LVTTL P15 " "Info: Pin D5M_FVAL uses I/O standard 3.3-V LVTTL at P15" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_FVAL } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_FVAL" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 126 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_FVAL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1462 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Info: Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { KEY[1] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 84 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1362 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_LVAL 3.3-V LVTTL L15 " "Info: Pin D5M_LVAL uses I/O standard 3.3-V LVTTL at L15" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_LVAL } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_LVAL" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 127 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_LVAL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1463 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[2\] 3.3-V LVTTL R11 " "Info: Pin D5M_D\[2\] uses I/O standard 3.3-V LVTTL at R11" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[2] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[2\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1426 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[3\] 3.3-V LVTTL T10 " "Info: Pin D5M_D\[3\] uses I/O standard 3.3-V LVTTL at T10" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[3] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[3\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1427 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[4\] 3.3-V LVTTL T11 " "Info: Pin D5M_D\[4\] uses I/O standard 3.3-V LVTTL at T11" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[4] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[4\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1428 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[5\] 3.3-V LVTTL R12 " "Info: Pin D5M_D\[5\] uses I/O standard 3.3-V LVTTL at R12" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[5] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[5\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1429 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[6\] 3.3-V LVTTL T12 " "Info: Pin D5M_D\[6\] uses I/O standard 3.3-V LVTTL at T12" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[6] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[6\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1430 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[7\] 3.3-V LVTTL R13 " "Info: Pin D5M_D\[7\] uses I/O standard 3.3-V LVTTL at R13" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[7] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[7\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1431 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[8\] 3.3-V LVTTL T13 " "Info: Pin D5M_D\[8\] uses I/O standard 3.3-V LVTTL at T13" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[8] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[8\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1432 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[9\] 3.3-V LVTTL T14 " "Info: Pin D5M_D\[9\] uses I/O standard 3.3-V LVTTL at T14" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[9] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[9\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1433 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[10\] 3.3-V LVTTL T15 " "Info: Pin D5M_D\[10\] uses I/O standard 3.3-V LVTTL at T15" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[10] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[10\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1434 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[11\] 3.3-V LVTTL F13 " "Info: Pin D5M_D\[11\] uses I/O standard 3.3-V LVTTL at F13" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[11] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[11\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1435 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[1\] 3.3-V LVTTL P11 " "Info: Pin D5M_D\[1\] uses I/O standard 3.3-V LVTTL at P11" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[1] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[1\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1425 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "D5M_D\[0\] 3.3-V LVTTL R10 " "Info: Pin D5M_D\[0\] uses I/O standard 3.3-V LVTTL at R10" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { D5M_D[0] } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "D5M_D\[0\]" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 125 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5M_D[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1424 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!d! pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone&nbsp;III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems)." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "1 " "Warning: Following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "I2C_SDAT a permanently disabled " "Info: Pin I2C_SDAT has a permanently disabled output enable" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "de_nano.v" "" { Text "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/de_nano.v" 105 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/" 0 { } { { 0 { 0 ""} 0 1449 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/DE_NANO.fit.smsg " "Info: Generated suppressed messages file D:/TERASIC_TEST/DE_NANO/DE_NANO_D5M_LTM/DE_NANO.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 58 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 58 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 04 11:16:33 2011 " "Info: Processing ended: Tue Jan 04 11:16:33 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:41 " "Info: Elapsed time: 00:00:41" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:46 " "Info: Total CPU time (on all processors): 00:00:46" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 04 11:16:35 2011 " "Info: Processing started: Tue Jan 04 11:16:35 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DE_NANO -c DE_NANO " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE_NANO -c DE_NANO" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 04 11:16:35 2011 " "Info: Processing started: Tue Jan 04 11:16:35 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DE_NANO -c DE_NANO " "Info: Command: quartus_sta DE_NANO -c DE_NANO" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Info: high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Info: low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_seo1 " "Info: Entity dcfifo_seo1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_se9:dffpipe9\|dffe10a*  " "Info: set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_se9:dffpipe9\|dffe10a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_re9:dffpipe6\|dffe7a*  " "Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_re9:dffpipe6\|dffe7a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "DE_NANO.SDC " "Info: Reading SDC File: 'DE_NANO.SDC'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL Clocks " "Info: Deriving PLL Clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -phase 180.00 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -phase 180.00 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -7.50 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -7.50 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Info: Clock uncertainty calculation is delayed until the next update_timing_netlist call" {  } {  } 0 0 "Clock uncertainty calculation is delayed until the next update_timing_netlist call" 0 0 "" 0 -1}
{ "Warning" "WSTA_FILTERS_COULD_NOT_BE_MATCHED" "" "Warning: At least one of the filters had some problems and could not be matched" { { "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED" "clk clock " "Warning: clk could not be matched with a clock" {  } {  } 0 0 "%1!s! could not be matched with a %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "At least one of the filters had some problems and could not be matched" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_input_delay -add_delay -clock \[get_clocks \{clk\}\] 1.500 \[all_inputs\] " "Warning: Ignored assignment: set_input_delay -add_delay -clock \[get_clocks \{clk\}\] 1.500 \[all_inputs\]" { { "Warning" "WSTA_NOT_AN_OBJECT_ID" "-clock " "Warning: Argument -clock is not an object ID" {  } {  } 0 0 "Argument %1!s! is not an object ID" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.557 \[get_ports \{DRAM_DQ*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.557 \[get_ports \{DRAM_DQ*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_DQ*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_DQ*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_ADDR*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_ADDR*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.820 \[get_ports \{DRAM_ADDR*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.820 \[get_ports \{DRAM_ADDR*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_FILTERS_COULD_NOT_BE_MATCHED" "" "Warning: At least one of the filters had some problems and could not be matched" { { "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED" "DRAM_*DQM port " "Warning: DRAM_*DQM could not be matched with a port" {  } {  } 0 0 "%1!s! could not be matched with a %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "At least one of the filters had some problems and could not be matched" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.652 \[get_ports \{DRAM_*DQM\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.652 \[get_ports \{DRAM_*DQM\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Positional argument <targets> \[get_ports \{DRAM_*DQM\}\] " "Warning: Positional argument <targets> with value \[get_ports \{DRAM_*DQM\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1} { "Warning" "WSTA_IO_ASSIGNMENT_ENTIRE_OBJECT_LIST_INVALID_TYPE" "\[get_ports \{DRAM_*DQM\}\] output " "Warning: Positional argument: object_list targets with value \[get_ports \{DRAM_*DQM\}\] contains no output ports" {  } {  } 0 0 "Positional argument: object_list targets with value %1!s! contains no %2!s! ports" 0 0 "" 0 -1} { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.781 \[get_ports \{DRAM_*DQM\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.781 \[get_ports \{DRAM_*DQM\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Positional argument <targets> \[get_ports \{DRAM_*DQM\}\] " "Warning: Positional argument <targets> with value \[get_ports \{DRAM_*DQM\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1} { "Warning" "WSTA_IO_ASSIGNMENT_ENTIRE_OBJECT_LIST_INVALID_TYPE" "\[get_ports \{DRAM_*DQM\}\] output " "Warning: Positional argument: object_list targets with value \[get_ports \{DRAM_*DQM\}\] contains no output ports" {  } {  } 0 0 "Positional argument: object_list targets with value %1!s! contains no %2!s! ports" 0 0 "" 0 -1} { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.494 \[get_ports \{DRAM_BA*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.494 \[get_ports \{DRAM_BA*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.806 \[get_ports \{DRAM_BA*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.806 \[get_ports \{DRAM_BA*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_RAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_RAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.779 \[get_ports \{DRAM_RAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.779 \[get_ports \{DRAM_RAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.513 \[get_ports \{DRAM_CAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.513 \[get_ports \{DRAM_CAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.787 \[get_ports \{DRAM_CAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.787 \[get_ports \{DRAM_CAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.628 \[get_ports \{DRAM_WE_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.628 \[get_ports \{DRAM_WE_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.672 \[get_ports \{DRAM_WE_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.672 \[get_ports \{DRAM_WE_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.492 \[get_ports \{DRAM_CKE\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.492 \[get_ports \{DRAM_CKE\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_CKE\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_CKE\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.544 \[get_ports \{DRAM_CS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.544 \[get_ports \{DRAM_CS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.756 \[get_ports \{DRAM_CS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.756 \[get_ports \{DRAM_CS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rCCD_PCLK " "Warning: Node: rCCD_PCLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_CCD_Config:u6\|mI2C_CTRL_CLK " "Warning: Node: I2C_CCD_Config:u6\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK " "Warning: Node: lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 4.284 " "Info: Worst-case setup slack is 4.284" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.284         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     4.284         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   13.795         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    13.795         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.363         0.000 CLOCK_50  " "Info:    15.363         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   35.536         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    35.536         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.048 " "Info: Worst-case hold slack is 0.048" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.048         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     0.048         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.140         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     0.140         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.146         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     0.146         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.360         0.000 CLOCK_50  " "Info:     0.360         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 6.291 " "Info: Worst-case recovery slack is 6.291" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.291         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     6.291         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.696         0.000 CLOCK_50  " "Info:    15.696         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.386         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    16.386         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   36.458         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    36.458         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.258 " "Info: Worst-case removal slack is 0.258" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.258         0.000 CLOCK_50  " "Info:     0.258         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.412         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     2.412         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.413         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     2.413         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.192         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     3.192         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.743 " "Info: Worst-case minimum pulse width slack is 4.743" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.743         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     4.743         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.570         0.000 CLOCK_50  " "Info:     9.570         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.744         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    19.744         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.746         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    19.746         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 80 synchronizer chains. " "Info: Report Metastability: Found 80 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n " "Info: Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 80 " "Info: Number of Synchronizer Chains Found: 80" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Info: Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Info: Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 15.576 ns " "Info: Worst Case Available Settling Time: 15.576 ns" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "Info: " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Info: Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " "Info:   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "EP4CE22F17C6 " "Warning: Timing characteristics of device EP4CE22F17C6 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "204 " "Info: Peak virtual memory: 204 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 04 11:16:40 2011 " "Info: Processing ended: Tue Jan 04 11:16:40 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rCCD_PCLK " "Warning: Node: rCCD_PCLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_CCD_Config:u6\|mI2C_CTRL_CLK " "Warning: Node: I2C_CCD_Config:u6\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK " "Warning: Node: lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 4.869 " "Info: Worst-case setup slack is 4.869" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.869         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     4.869         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.395         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    14.395         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.809         0.000 CLOCK_50  " "Info:    15.809         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   36.023         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    36.023         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.041 " "Info: Worst-case hold slack is 0.041" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.041         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     0.041         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.123         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     0.123         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.137         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     0.137         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.314         0.000 CLOCK_50  " "Info:     0.314         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 6.700 " "Info: Worst-case recovery slack is 6.700" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.700         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     6.700         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.151         0.000 CLOCK_50  " "Info:    16.151         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.784         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    16.784         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   36.854         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    36.854         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.283 " "Info: Worst-case removal slack is 0.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.283         0.000 CLOCK_50  " "Info:     0.283         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.162         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     2.162         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.165         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     2.165         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.876         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     2.876         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.739 " "Info: Worst-case minimum pulse width slack is 4.739" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.739         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     4.739         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.551         0.000 CLOCK_50  " "Info:     9.551         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.740         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    19.740         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.743         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    19.743         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 80 synchronizer chains. " "Info: Report Metastability: Found 80 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n " "Info: Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 80 " "Info: Number of Synchronizer Chains Found: 80" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Info: Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Info: Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 16.047 ns " "Info: Worst Case Available Settling Time: 16.047 ns" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "Info: " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Info: Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " "Info:   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "EP4CE22F17C6 " "Warning: Timing characteristics of device EP4CE22F17C6 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rCCD_PCLK " "Warning: Node: rCCD_PCLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_CCD_Config:u6\|mI2C_CTRL_CLK " "Warning: Node: I2C_CCD_Config:u6\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK " "Warning: Node: lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 6.732 " "Info: Worst-case setup slack is 6.732" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.732         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     6.732         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.435         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    16.435         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.382         0.000 CLOCK_50  " "Info:    17.382         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   37.473         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    37.473         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.013 " "Info: Worst-case hold slack is 0.013" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.013         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     0.013         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.039         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     0.039         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.065         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     0.065         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.187         0.000 CLOCK_50  " "Info:     0.187         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 7.780 " "Info: Worst-case recovery slack is 7.780" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    7.780         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     7.780         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.510         0.000 CLOCK_50  " "Info:    17.510         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.850         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    17.850         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   37.860         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    37.860         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Critical Warning: Timing requirements not met" {  } {  } 1 0 "Timing requirements not met" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal -0.016 " "Info: Worst-case removal slack is -0.016" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.016        -0.256 CLOCK_50  " "Info:    -0.016        -0.256 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.420         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     1.420         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.421         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     1.421         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.920         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     1.920         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.750 " "Info: Worst-case minimum pulse width slack is 4.750" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.750         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     4.750         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.282         0.000 CLOCK_50  " "Info:     9.282         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.749         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    19.749         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.752         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    19.752         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 80 synchronizer chains. " "Info: Report Metastability: Found 80 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n " "Info: Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 80 " "Info: Number of Synchronizer Chains Found: 80" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Info: Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Info: Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.521 ns " "Info: Worst Case Available Settling Time: 17.521 ns" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "Info: " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Info: Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " "Info:   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 58 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 58 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "225 " "Info: Peak virtual memory: 225 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 04 11:16:49 2011 " "Info: Processing ended: Tue Jan 04 11:16:49 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Info: Total CPU time (on all processors): 00:00:13" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 181 s " "Info: Quartus II Full Compilation was successful. 0 errors, 181 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
