{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 04 11:18:45 2011 " "Info: Processing started: Tue Jan 04 11:18:45 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DE_NANO -c DE_NANO " "Info: Command: quartus_sta DE_NANO -c DE_NANO" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Info: high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Info: low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_seo1 " "Info: Entity dcfifo_seo1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_se9:dffpipe9\|dffe10a*  " "Info: set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_se9:dffpipe9\|dffe10a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_re9:dffpipe6\|dffe7a*  " "Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_re9:dffpipe6\|dffe7a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "DE_NANO.SDC " "Info: Reading SDC File: 'DE_NANO.SDC'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL Clocks " "Info: Deriving PLL Clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -phase 180.00 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -phase 180.00 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -7.50 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\} " "Info: create_generated_clock -source \{u10\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -7.50 -duty_cycle 50.00 -name \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\} \{u10\|altpll_component\|auto_generated\|pll1\|clk\[4\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Info: Clock uncertainty calculation is delayed until the next update_timing_netlist call" {  } {  } 0 0 "Clock uncertainty calculation is delayed until the next update_timing_netlist call" 0 0 "" 0 -1}
{ "Warning" "WSTA_FILTERS_COULD_NOT_BE_MATCHED" "" "Warning: At least one of the filters had some problems and could not be matched" { { "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED" "clk clock " "Warning: clk could not be matched with a clock" {  } {  } 0 0 "%1!s! could not be matched with a %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "At least one of the filters had some problems and could not be matched" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_input_delay -add_delay -clock \[get_clocks \{clk\}\] 1.500 \[all_inputs\] " "Warning: Ignored assignment: set_input_delay -add_delay -clock \[get_clocks \{clk\}\] 1.500 \[all_inputs\]" { { "Warning" "WSTA_NOT_AN_OBJECT_ID" "-clock " "Warning: Argument -clock is not an object ID" {  } {  } 0 0 "Argument %1!s! is not an object ID" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.557 \[get_ports \{DRAM_DQ*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.557 \[get_ports \{DRAM_DQ*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_DQ*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_DQ*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_ADDR*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_ADDR*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.820 \[get_ports \{DRAM_ADDR*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.820 \[get_ports \{DRAM_ADDR*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_FILTERS_COULD_NOT_BE_MATCHED" "" "Warning: At least one of the filters had some problems and could not be matched" { { "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED" "DRAM_*DQM port " "Warning: DRAM_*DQM could not be matched with a port" {  } {  } 0 0 "%1!s! could not be matched with a %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "At least one of the filters had some problems and could not be matched" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.652 \[get_ports \{DRAM_*DQM\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.652 \[get_ports \{DRAM_*DQM\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Positional argument <targets> \[get_ports \{DRAM_*DQM\}\] " "Warning: Positional argument <targets> with value \[get_ports \{DRAM_*DQM\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1} { "Warning" "WSTA_IO_ASSIGNMENT_ENTIRE_OBJECT_LIST_INVALID_TYPE" "\[get_ports \{DRAM_*DQM\}\] output " "Warning: Positional argument: object_list targets with value \[get_ports \{DRAM_*DQM\}\] contains no output ports" {  } {  } 0 0 "Positional argument: object_list targets with value %1!s! contains no %2!s! ports" 0 0 "" 0 -1} { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.781 \[get_ports \{DRAM_*DQM\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.781 \[get_ports \{DRAM_*DQM\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Positional argument <targets> \[get_ports \{DRAM_*DQM\}\] " "Warning: Positional argument <targets> with value \[get_ports \{DRAM_*DQM\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1} { "Warning" "WSTA_IO_ASSIGNMENT_ENTIRE_OBJECT_LIST_INVALID_TYPE" "\[get_ports \{DRAM_*DQM\}\] output " "Warning: Positional argument: object_list targets with value \[get_ports \{DRAM_*DQM\}\] contains no output ports" {  } {  } 0 0 "Positional argument: object_list targets with value %1!s! contains no %2!s! ports" 0 0 "" 0 -1} { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.494 \[get_ports \{DRAM_BA*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.494 \[get_ports \{DRAM_BA*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.806 \[get_ports \{DRAM_BA*\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.806 \[get_ports \{DRAM_BA*\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_RAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.521 \[get_ports \{DRAM_RAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.779 \[get_ports \{DRAM_RAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.779 \[get_ports \{DRAM_RAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.513 \[get_ports \{DRAM_CAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.513 \[get_ports \{DRAM_CAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.787 \[get_ports \{DRAM_CAS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.787 \[get_ports \{DRAM_CAS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.628 \[get_ports \{DRAM_WE_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.628 \[get_ports \{DRAM_WE_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.672 \[get_ports \{DRAM_WE_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.672 \[get_ports \{DRAM_WE_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.492 \[get_ports \{DRAM_CKE\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.492 \[get_ports \{DRAM_CKE\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_CKE\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.808 \[get_ports \{DRAM_CKE\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.544 \[get_ports \{DRAM_CS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -max -clock \[get_clocks \{clk_dram\}\] 1.544 \[get_ports \{DRAM_CS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT" "set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.756 \[get_ports \{DRAM_CS_N\}\] " "Warning: Ignored assignment: set_output_delay -add_delay -min -clock \[get_clocks \{clk_dram\}\] -0.756 \[get_ports \{DRAM_CS_N\}\]" { { "Warning" "WSTA_COLLECTION_MANAGER_EMPTY_COLLECTION" "Argument -clock \[get_clocks \{clk_dram\}\] " "Warning: Argument -clock with value \[get_clocks \{clk_dram\}\] contains zero elements" {  } {  } 0 0 "%1!s! with value %2!s! contains zero elements" 0 0 "" 0 -1}  } {  } 0 0 "Ignored assignment: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rCCD_PCLK " "Warning: Node: rCCD_PCLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_CCD_Config:u6\|mI2C_CTRL_CLK " "Warning: Node: I2C_CCD_Config:u6\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK " "Warning: Node: lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.912 " "Info: Worst-case setup slack is 3.912" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.912         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     3.912         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   13.239         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    13.239         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.716         0.000 CLOCK_50  " "Info:    15.716         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   35.066         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    35.066         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.044 " "Info: Worst-case hold slack is 0.044" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.044         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     0.044         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.322         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     0.322         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.324         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     0.324         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.358         0.000 CLOCK_50  " "Info:     0.358         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 5.772 " "Info: Worst-case recovery slack is 5.772" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    5.772         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     5.772         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.336         0.000 CLOCK_50  " "Info:    15.336         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.866         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    15.866         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   35.939         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    35.939         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.536 " "Info: Worst-case removal slack is 0.536" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.536         0.000 CLOCK_50  " "Info:     0.536         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.875         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     2.875         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.892         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     2.892         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.230         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     3.230         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.744 " "Info: Worst-case minimum pulse width slack is 4.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.744         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     4.744         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.567         0.000 CLOCK_50  " "Info:     9.567         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.744         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    19.744         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.747         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    19.747         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 80 synchronizer chains. " "Info: Report Metastability: Found 80 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n " "Info: Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 80 " "Info: Number of Synchronizer Chains Found: 80" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Info: Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Info: Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 15.820 ns " "Info: Worst Case Available Settling Time: 15.820 ns" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "Info: " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Info: Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " "Info:   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "EP4CE22F17C6 " "Warning: Timing characteristics of device EP4CE22F17C6 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rCCD_PCLK " "Warning: Node: rCCD_PCLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_CCD_Config:u6\|mI2C_CTRL_CLK " "Warning: Node: I2C_CCD_Config:u6\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK " "Warning: Node: lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 4.531 " "Info: Worst-case setup slack is 4.531" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.531         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     4.531         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   13.837         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    13.837         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.168         0.000 CLOCK_50  " "Info:    16.168         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   35.605         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    35.605         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.040 " "Info: Worst-case hold slack is 0.040" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.040         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     0.040         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.279         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     0.279         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.279         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     0.279         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.312         0.000 CLOCK_50  " "Info:     0.312         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 6.236 " "Info: Worst-case recovery slack is 6.236" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.236         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     6.236         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.832         0.000 CLOCK_50  " "Info:    15.832         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.320         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    16.320         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   36.390         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    36.390         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.539 " "Info: Worst-case removal slack is 0.539" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.539         0.000 CLOCK_50  " "Info:     0.539         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.590         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     2.590         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.607         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     2.607         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.933         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     2.933         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.740 " "Info: Worst-case minimum pulse width slack is 4.740" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.740         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     4.740         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.531         0.000 CLOCK_50  " "Info:     9.531         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.739         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    19.739         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.744         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    19.744         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 80 synchronizer chains. " "Info: Report Metastability: Found 80 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n " "Info: Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 80 " "Info: Number of Synchronizer Chains Found: 80" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Info: Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Info: Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 16.249 ns " "Info: Worst Case Available Settling Time: 16.249 ns" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "Info: " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Info: Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " "Info:   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "EP4CE22F17C6 " "Warning: Timing characteristics of device EP4CE22F17C6 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rCCD_PCLK " "Warning: Node: rCCD_PCLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "I2C_CCD_Config:u6\|mI2C_CTRL_CLK " "Warning: Node: I2C_CCD_Config:u6\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK " "Warning: Node: lcd_3wire_config:u8\|I2S_Controller:u0\|mI2S_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -setup 0.090" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -rise_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}\] -fall_to \[get_clocks \{CLOCK_50\}\] -hold 0.060" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -rise_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -fall_to \[get_clocks \{u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 6.412 " "Info: Worst-case setup slack is 6.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.412         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     6.412         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.107         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    16.107         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.498         0.000 CLOCK_50  " "Info:    17.498         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   37.187         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    37.187         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.010 " "Info: Worst-case hold slack is 0.010" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.010         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     0.010         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.156         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     0.156         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.158         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     0.158         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.186         0.000 CLOCK_50  " "Info:     0.186         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 7.445 " "Info: Worst-case recovery slack is 7.445" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    7.445         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     7.445         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.324         0.000 CLOCK_50  " "Info:    17.324         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.513         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    17.513         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   37.525         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    37.525         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.232 " "Info: Worst-case removal slack is 0.232" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.232         0.000 CLOCK_50  " "Info:     0.232         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.695         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:     1.695         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.701         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     1.701         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.870         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:     1.870         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.752 " "Info: Worst-case minimum pulse width slack is 4.752" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.752         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\]  " "Info:     4.752         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[3\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.297         0.000 CLOCK_50  " "Info:     9.297         0.000 CLOCK_50 " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.745         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\]  " "Info:    19.745         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[1\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.752         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "Info:    19.752         0.000 u10\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 80 synchronizer chains. " "Info: Report Metastability: Found 80 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n " "Info: Typical MTBF of Design is 1e+009 years or 3.15e+016 seconds.\n" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 80 " "Info: Number of Synchronizer Chains Found: 80" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Info: Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Info: Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.624 ns " "Info: Worst Case Available Settling Time: 17.624 ns" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "Info: " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Info: Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " "Info:   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 57 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 57 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "225 " "Info: Peak virtual memory: 225 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 04 11:18:58 2011 " "Info: Processing ended: Tue Jan 04 11:18:58 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Info: Total CPU time (on all processors): 00:00:13" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
