Hierarchy | Input | Constant Input | Unused Input | Floating Input | Output | Constant Output | Unused Output | Floating Output | Bidir | Constant Bidir | Unused Bidir | Input only Bidir | Output only Bidir
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u8|u0 | 19 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0
u8 | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0
u7 | 34 | 0 | 8 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u6|u0 | 35 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0
u6 | 5 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|ws_dgrp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|ws_bwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|ws_brp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|rs_dgwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|rs_bwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|rs_brp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|fifo_ram | 40 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|wrptr_gp | 3 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|wrptr_g1p | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|rdptr_g1p | 3 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2|dcfifo_component|auto_generated | 21 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo2 | 21 | 0 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|ws_dgrp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|ws_bwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|ws_brp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|rs_dgwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|rs_bwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|rs_brp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|fifo_ram | 40 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|wrptr_gp | 3 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|wrptr_g1p | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|rdptr_g1p | 3 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1|dcfifo_component|auto_generated | 21 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|read_fifo1 | 21 | 0 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|ws_dgrp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|ws_bwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|ws_brp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|rs_dgwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|rs_bwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|rs_brp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|fifo_ram | 40 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|wrptr_gp | 3 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|wrptr_g1p | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|rdptr_g1p | 3 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2|dcfifo_component|auto_generated | 21 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo2 | 21 | 0 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|ws_dgrp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|ws_bwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|ws_brp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|rs_dgwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|rs_bwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|rs_brp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|fifo_ram | 40 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|wrptr_gp | 3 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|wrptr_g1p | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|rdptr_g1p | 3 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin | 10 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1|dcfifo_component|auto_generated | 21 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|write_fifo1 | 21 | 0 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|data_path1 | 20 | 2 | 0 | 2 | 18 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
u5|command1 | 35 | 0 | 2 | 0 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u5|control1 | 30 | 1 | 0 | 1 | 32 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u5 | 267 | 224 | 1 | 224 | 54 | 224 | 224 | 224 | 16 | 0 | 0 | 0 | 0
u10|altpll_component|auto_generated | 2 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u10 | 1 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u3|L1|altshift_taps_component|auto_generated|cntr1|cmpr4 | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u3|L1|altshift_taps_component|auto_generated|cntr1 | 2 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u3|L1|altshift_taps_component|auto_generated|altsyncram2 | 59 | 1 | 0 | 1 | 36 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u3|L1|altshift_taps_component|auto_generated | 14 | 0 | 0 | 0 | 48 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u3|L1 | 14 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u3 | 48 | 1 | 0 | 1 | 37 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u2 | 18 | 0 | 0 | 0 | 77 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u1 | 2 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0