--dcfifo_mixed_widths ADD_RAM_OUTPUT_REGISTER="OFF" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone III" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=512 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTH_R=16 LPM_WIDTHU=9 LPM_WIDTHU_R=9 OVERFLOW_CHECKING="ON" RAM_BLOCK_TYPE="M4K" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=M4K" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 10.1SP1 cbx_a_gray2bin 2011:01:19:21:13:40:SJ cbx_a_graycounter 2011:01:19:21:13:40:SJ cbx_altdpram 2011:01:19:21:13:40:SJ cbx_altsyncram 2011:01:19:21:13:40:SJ cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_dcfifo 2011:01:19:21:13:40:SJ cbx_fifo_common 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_compare 2011:01:19:21:13:40:SJ cbx_lpm_counter 2011:01:19:21:13:40:SJ cbx_lpm_decode 2011:01:19:21:13:40:SJ cbx_lpm_mux 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_scfifo 2011:01:19:21:13:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ cbx_stratixiii 2011:01:19:21:13:40:SJ cbx_stratixv 2011:01:19:21:13:40:SJ cbx_util_mgl 2011:01:19:21:13:40:SJ  VERSION_END


-- Copyright (C) 1991-2011 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION a_gray2bin_tgb (gray[9..0])
RETURNS ( bin[9..0]);
FUNCTION a_graycounter_s57 (aclr, clock, cnt_en)
RETURNS ( q[9..0]);
FUNCTION a_graycounter_ojc (aclr, clock, cnt_en)
RETURNS ( q[9..0]);
FUNCTION a_graycounter_njc (aclr, clock, cnt_en)
RETURNS ( q[9..0]);
FUNCTION altsyncram_de51 (aclr1, address_a[8..0], address_b[8..0], addressstall_b, clock0, clock1, clocken1, data_a[15..0], wren_a)
RETURNS ( q_b[15..0]);
FUNCTION dffpipe_oe9 (clock, clrn, d[9..0])
RETURNS ( q[9..0]);
FUNCTION alt_synch_pipe_qld (clock, clrn, d[9..0])
RETURNS ( q[9..0]);
FUNCTION alt_synch_pipe_rld (clock, clrn, d[9..0])
RETURNS ( q[9..0]);
FUNCTION cmpr_e66 (dataa[9..0], datab[9..0])
RETURNS ( aeb);

--synthesis_resources = lut 22 M9K 1 reg 142 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 2;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe19|dffe20a;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe19|dffe20a* "";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe16|dffe17a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe16|dffe17a* """;

SUBDESIGN dcfifo_v5o1
( 
	aclr	:	input;
	data[15..0]	:	input;
	q[15..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdreq	:	input;
	rdusedw[8..0]	:	output;
	wrclk	:	input;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[8..0]	:	output;
) 
VARIABLE 
	rdptr_g_gray2bin : a_gray2bin_tgb;
	rs_dgwp_gray2bin : a_gray2bin_tgb;
	wrptr_g_gray2bin : a_gray2bin_tgb;
	ws_dgrp_gray2bin : a_gray2bin_tgb;
	rdptr_g1p : a_graycounter_s57;
	wrptr_g1p : a_graycounter_ojc;
	wrptr_gp : a_graycounter_njc;
	fifo_ram : altsyncram_de51;
	delayed_wrptr_g[9..0] : dffe;
	rdptr_g[9..0] : dffe;
	rs_brp : dffpipe_oe9;
	rs_bwp : dffpipe_oe9;
	rs_dgwp : alt_synch_pipe_qld;
	ws_brp : dffpipe_oe9;
	ws_bwp : dffpipe_oe9;
	ws_dgrp : alt_synch_pipe_rld;
	rdusedw_sub_dataa[9..0]	:	WIRE;
	rdusedw_sub_datab[9..0]	:	WIRE;
	rdusedw_sub_result[9..0]	:	WIRE;
	wrusedw_sub_dataa[9..0]	:	WIRE;
	wrusedw_sub_datab[9..0]	:	WIRE;
	wrusedw_sub_result[9..0]	:	WIRE;
	rdempty_eq_comp : cmpr_e66;
	wrfull_eq_comp : cmpr_e66;
	int_rdempty	: WIRE;
	int_wrfull	: WIRE;
	ram_address_a[8..0]	: WIRE;
	ram_address_b[8..0]	: WIRE;
	valid_rdreq	: WIRE;
	valid_wrreq	: WIRE;
	wrptr_gs[9..0]	: WIRE;

BEGIN 
	rdptr_g_gray2bin.gray[9..0] = rdptr_g[9..0].q;
	rs_dgwp_gray2bin.gray[9..0] = rs_dgwp.q[9..0];
	wrptr_g_gray2bin.gray[9..0] = wrptr_gp.q[9..0];
	ws_dgrp_gray2bin.gray[9..0] = ws_dgrp.q[9..0];
	rdptr_g1p.aclr = aclr;
	rdptr_g1p.clock = rdclk;
	rdptr_g1p.cnt_en = valid_rdreq;
	wrptr_g1p.aclr = aclr;
	wrptr_g1p.clock = wrclk;
	wrptr_g1p.cnt_en = valid_wrreq;
	wrptr_gp.aclr = aclr;
	wrptr_gp.clock = wrclk;
	wrptr_gp.cnt_en = valid_wrreq;
	fifo_ram.aclr1 = aclr;
	fifo_ram.address_a[] = ram_address_a[];
	fifo_ram.address_b[] = ram_address_b[];
	fifo_ram.addressstall_b = (! valid_rdreq);
	fifo_ram.clock0 = wrclk;
	fifo_ram.clock1 = rdclk;
	fifo_ram.clocken1 = valid_rdreq;
	fifo_ram.data_a[] = data[];
	fifo_ram.wren_a = valid_wrreq;
	delayed_wrptr_g[].clk = wrclk;
	delayed_wrptr_g[].clrn = (! aclr);
	delayed_wrptr_g[].d = wrptr_gp.q[];
	rdptr_g[].clk = rdclk;
	rdptr_g[].clrn = (! aclr);
	rdptr_g[].d = rdptr_g1p.q[];
	rdptr_g[].ena = valid_rdreq;
	rs_brp.clock = rdclk;
	rs_brp.clrn = (! aclr);
	rs_brp.d[] = rdptr_g_gray2bin.bin[];
	rs_bwp.clock = rdclk;
	rs_bwp.clrn = (! aclr);
	rs_bwp.d[] = rs_dgwp_gray2bin.bin[];
	rs_dgwp.clock = rdclk;
	rs_dgwp.clrn = (! aclr);
	rs_dgwp.d[] = delayed_wrptr_g[].q;
	ws_brp.clock = wrclk;
	ws_brp.clrn = (! aclr);
	ws_brp.d[] = ws_dgrp_gray2bin.bin[];
	ws_bwp.clock = wrclk;
	ws_bwp.clrn = (! aclr);
	ws_bwp.d[] = wrptr_g_gray2bin.bin[];
	ws_dgrp.clock = wrclk;
	ws_dgrp.clrn = (! aclr);
	ws_dgrp.d[] = rdptr_g[].q;
	rdusedw_sub_result[] = rdusedw_sub_dataa[] - rdusedw_sub_datab[];
	rdusedw_sub_dataa[] = rs_bwp.q[];
	rdusedw_sub_datab[] = rs_brp.q[];
	wrusedw_sub_result[] = wrusedw_sub_dataa[] - wrusedw_sub_datab[];
	wrusedw_sub_dataa[] = ws_bwp.q[];
	wrusedw_sub_datab[] = ws_brp.q[];
	rdempty_eq_comp.dataa[] = rs_dgwp.q[];
	rdempty_eq_comp.datab[] = rdptr_g[].q;
	wrfull_eq_comp.dataa[] = ws_dgrp.q[];
	wrfull_eq_comp.datab[] = wrptr_gs[];
	int_rdempty = rdempty_eq_comp.aeb;
	int_wrfull = wrfull_eq_comp.aeb;
	q[] = fifo_ram.q_b[];
	ram_address_a[] = ( (wrptr_gp.q[9..9] $ wrptr_gp.q[8..8]), wrptr_gp.q[7..0]);
	ram_address_b[] = ( (rdptr_g1p.q[9..9] $ rdptr_g1p.q[8..8]), rdptr_g1p.q[7..0]);
	rdempty = int_rdempty;
	rdusedw[] = ( rdusedw_sub_result[8..0]);
	valid_rdreq = (rdreq & (! int_rdempty));
	valid_wrreq = (wrreq & (! int_wrfull));
	wrfull = int_wrfull;
	wrptr_gs[] = ( (! wrptr_gp.q[9..9]), (! wrptr_gp.q[8..8]), wrptr_gp.q[7..0]);
	wrusedw[] = ( wrusedw_sub_result[8..0]);
	ASSERT (0) 
	REPORT "Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2"
	SEVERITY WARNING;
	ASSERT (0) 
	REPORT "Device family Cyclone III does not have M4K blocks -- using available memory blocks"
	SEVERITY WARNING;
END;
--VALID FILE
