// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// ============================================================================
//           
//  Terasic Technologies Inc
//  9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//  
//  
//                     web: http://www.terasic.com/  
//                     email: support@terasic.com
//
// ============================================================================
//Date:  Thu Jul 11 11:26:45 2013
// ============================================================================

//`define ENABLE_HPS
//`define ENABLE_USB

module DE1_SoC_CAMERA(

      ///////// ADC /////////
      inout              ADC_CS_N,
      output             ADC_DIN,
      input              ADC_DOUT,
      output             ADC_SCLK,

      ///////// AUD /////////
      input              AUD_ADCDAT,
      inout              AUD_ADCLRCK,
      inout              AUD_BCLK,
      output             AUD_DACDAT,
      inout              AUD_DACLRCK,
      output             AUD_XCK,

      ///////// CLOCK2 /////////
      input              CLOCK2_50,

      ///////// CLOCK3 /////////
      input              CLOCK3_50,

      ///////// CLOCK4 /////////
      input              CLOCK4_50,

      ///////// CLOCK /////////
      input              CLOCK_50,

      ///////// DRAM /////////
      output      [12:0] DRAM_ADDR,
      output      [1:0]  DRAM_BA,
      output             DRAM_CAS_N,
      output             DRAM_CKE,
      output             DRAM_CLK,
      output             DRAM_CS_N,
      inout       [15:0] DRAM_DQ,
      output             DRAM_LDQM,
      output             DRAM_RAS_N,
      output             DRAM_UDQM,
      output             DRAM_WE_N,

      ///////// FAN /////////
      output             FAN_CTRL,

      ///////// FPGA /////////
      output             FPGA_I2C_SCLK,
      inout              FPGA_I2C_SDAT,

      ///////// GPIO /////////
      inout     [35:0]   GPIO_0,
	
      ///////// HEX0 /////////
      output      [6:0]  HEX0,

      ///////// HEX1 /////////
      output      [6:0]  HEX1,

      ///////// HEX2 /////////
      output      [6:0]  HEX2,

      ///////// HEX3 /////////
      output      [6:0]  HEX3,

      ///////// HEX4 /////////
      output      [6:0]  HEX4,

      ///////// HEX5 /////////
      output      [6:0]  HEX5,

`ifdef ENABLE_HPS
      ///////// HPS /////////
      input              HPS_CONV_USB_N,
      output      [14:0] HPS_DDR3_ADDR,
      output      [2:0]  HPS_DDR3_BA,
      output             HPS_DDR3_CAS_N,
      output             HPS_DDR3_CKE,
      output             HPS_DDR3_CK_N,
      output             HPS_DDR3_CK_P,
      output             HPS_DDR3_CS_N,
      output      [3:0]  HPS_DDR3_DM,
      inout       [31:0] HPS_DDR3_DQ,
      inout       [3:0]  HPS_DDR3_DQS_N,
      inout       [3:0]  HPS_DDR3_DQS_P,
      output             HPS_DDR3_ODT,
      output             HPS_DDR3_RAS_N,
      output             HPS_DDR3_RESET_N,
      input              HPS_DDR3_RZQ,
      output             HPS_DDR3_WE_N,
      output             HPS_ENET_GTX_CLK,
      inout              HPS_ENET_INT_N,
      output             HPS_ENET_MDC,
      inout              HPS_ENET_MDIO,
      input              HPS_ENET_RX_CLK,
      input       [3:0]  HPS_ENET_RX_DATA,
      input              HPS_ENET_RX_DV,
      output      [3:0]  HPS_ENET_TX_DATA,
      output             HPS_ENET_TX_EN,
      inout       [3:0]  HPS_FLASH_DATA,
      output             HPS_FLASH_DCLK,
      output             HPS_FLASH_NCSO,
      inout              HPS_GSENSOR_INT,
      inout              HPS_I2C1_SCLK,
      inout              HPS_I2C1_SDAT,
      inout              HPS_I2C2_SCLK,
      inout              HPS_I2C2_SDAT,
      inout              HPS_I2C_CONTROL,
      inout              HPS_KEY,
      inout              HPS_LED,
      inout              HPS_LTC_GPIO,
      output             HPS_SD_CLK,
      inout              HPS_SD_CMD,
      inout       [3:0]  HPS_SD_DATA,
      output             HPS_SPIM_CLK,
      input              HPS_SPIM_MISO,
      output             HPS_SPIM_MOSI,
      inout              HPS_SPIM_SS,
      input              HPS_UART_RX,
      output             HPS_UART_TX,
      input              HPS_USB_CLKOUT,
      inout       [7:0]  HPS_USB_DATA,
      input              HPS_USB_DIR,
      input              HPS_USB_NXT,
      output             HPS_USB_STP,
`endif /*ENABLE_HPS*/

      ///////// IRDA /////////
      input              IRDA_RXD,
      output             IRDA_TXD,

      ///////// KEY /////////
      input       [3:0]  KEY,

      ///////// LEDR /////////
      output      [9:0]  LEDR,

      ///////// PS2 /////////
      inout              PS2_CLK,
      inout              PS2_CLK2,
      inout              PS2_DAT,
      inout              PS2_DAT2,

      ///////// SW /////////
      input       [9:0]  SW,

      ///////// TD /////////
      input              TD_CLK27,
      input      [7:0]   TD_DATA,
      input              TD_HS,
      output             TD_RESET_N,
      input              TD_VS,

`ifdef ENABLE_USB
      ///////// USB /////////
      input              USB_B2_CLK,
      inout       [7:0]  USB_B2_DATA,
      output             USB_EMPTY,
      output             USB_FULL,
      input              USB_OE_N,
      input              USB_RD_N,
      input              USB_RESET_N,
      inout              USB_SCL,
      inout              USB_SDA,
      input              USB_WR_N,
`endif /*ENABLE_USB*/

      ///////// VGA /////////
      output      [7:0]  VGA_B,
      output             VGA_BLANK_N,
      output             VGA_CLK,
      output      [7:0]  VGA_G,
      output             VGA_HS,
      output      [7:0]  VGA_R,
      output             VGA_SYNC_N,
      output             VGA_VS,
		
		//////////// GPIO1, GPIO1 connect to D5M - 5M Pixel Camera //////////
	   input		   [11:0] D5M_D,
      input		          D5M_FVAL,
      input		          D5M_LVAL,
      input		          D5M_PIXLCLK,
      output		       D5M_RESET_N,
      output		       D5M_SCLK,
      inout		          D5M_SDATA,
      input		          D5M_STROBE,
      output		       D5M_TRIGGER,
      output		       D5M_XCLKIN
);
//=======================================================
//  REG/WIRE declarations
//=======================================================

wire system_reset_n;

wire DLY_RST_1;
wire DLY_RST_3;

//=======================================================
//  Structural coding
//=======================================================



//reset signals
Reset_Delay			Reset_Delay_inst(
							.iCLK(CLOCK_50),
							.iRST(KEY[0]),
							.oRST_0(),
							.oRST_1(DLY_RST_1),
							.oRST_2(),
							.oRST_3(DLY_RST_3), //auto-start start point
							.oRST_4()  //auto-start end point
						);

    D5M_VIP_QSYS u0 (
        .clk_50                                    (CLOCK_50),                                    //                   clk_50_clk_in.clk
        .reset_n                                   (KEY[0]),                                   //             clk_50_clk_in_reset.reset_n
		  
			// sdram
        .zs_addr_from_the_sdram                    (DRAM_ADDR),                    //                      sdram_wire.addr
        .zs_ba_from_the_sdram                      (DRAM_BA),                      //                                .ba
        .zs_cas_n_from_the_sdram                   (DRAM_CAS_N),                   //                                .cas_n
        .zs_cke_from_the_sdram                     (DRAM_CKE),                     //                                .cke
        .zs_cs_n_from_the_sdram                    (DRAM_CS_N),                    //                                .cs_n
        .zs_dq_to_and_from_the_sdram               (DRAM_DQ),               //                                .dq
        .zs_dqm_from_the_sdram                     ({DRAM_UDQM, DRAM_LDQM}),                     //                                .dqm
        .zs_ras_n_from_the_sdram                   (DRAM_RAS_N),                   //                                .ras_n
        .zs_we_n_from_the_sdram                    (DRAM_WE_N),                    //                                .we_n
		  
        .clk_sdram_clk                             (DRAM_CLK),                             //                       clk_sdram.clk
        .clk_vga_clk                               (disp_clk),                               //                         clk_vga.clk
//        .ledr_external_connection_export           (LEDR),           //        ledr_external_connection.export
//        .key_external_connection_export            (KEY),            //         key_external_connection.export
//        .sw_external_connection_export             (SW),             //          sw_external_connection.export
		  
			// VGA
        .alt_vip_itc_0_clocked_video_vid_clk       (disp_clk),       //     alt_vip_itc_0_clocked_video.vid_clk
        .alt_vip_itc_0_clocked_video_vid_data      (disp_data),      //                                .vid_data
        .alt_vip_itc_0_clocked_video_underflow     (),     //                                .underflow
        .alt_vip_itc_0_clocked_video_vid_datavalid (), //                                .vid_datavalid
        .alt_vip_itc_0_clocked_video_vid_v_sync    (disp_vs),    //                                .vid_v_sync
        .alt_vip_itc_0_clocked_video_vid_h_sync    (disp_hs),    //                                .vid_h_sync
        .alt_vip_itc_0_clocked_video_vid_f         (),         //                                .vid_f
        .alt_vip_itc_0_clocked_video_vid_h         (),         //                                .vid_h
        .alt_vip_itc_0_clocked_video_vid_v         (),         //                                .vid_v
		  
		  // D5M
        .d5m_conduit_end_D                         (D5M_D),                         //                 d5m_conduit_end.D
        .d5m_conduit_end_FVAL                      (D5M_FVAL),                      //                                .FVAL
        .d5m_conduit_end_LVAL                      (D5M_LVAL),                      //                                .LVAL
        .d5m_conduit_end_PIXCLK                    (D5M_PIXLCLK),                     //                                .PIXCLK
        .d5m_xclkin_clk                            (D5M_XCLKIN),                            //                       d5m_xclkin.clk
//        .d5m_i2c_sclk_external_connection_export   (D5M_SCLK),   // d5m_i2c_sclk_external_connection.export
//        .d5m_i2c_sdat_external_connection_export   (D5M_SDATA),   // d5m_i2c_sdat_external_connection.export
//        .d5m_trigger_external_connection_export    (D5M_TRIGGER),    //  d5m_trigger_external_connection.export
//        .d5m_reset_n_external_connection_export    (D5M_RESET_N)     //  d5m_reset_n_external_connection.export
		  
    );
	 

//	input 		          		D5M_STROBE,
	
/////////////////////////////
// VGA TX
wire [23:0]	disp_data;
wire			disp_clk;
wire			disp_hs;
wire			disp_vs;

assign VGA_CLK						= ~disp_clk;
assign {VGA_R, VGA_G, VGA_B}	= disp_data;
assign VGA_HS						= disp_hs;
assign VGA_VS						= disp_vs;	
assign VGA_BLANK_N 				= 1'b1;
assign VGA_SYNC_N 				= 1'b0;

///////////////////////////////////////////////
//D5M I2C control
I2C_CCD_Config 		i2c_config_inst	(	//	Host Side
							.iCLK(CLOCK_50),
							.iRST_N(DLY_RST_3),
							.iZOOM_MODE_SW(SW[1]),
							.iEXPOSURE_ADJ(KEY[1]),
							.iEXPOSURE_DEC_p(SW[0]),							
							//	I2C Side
							.I2C_SCLK(D5M_SCLK),
							.I2C_SDAT(D5M_SDATA)
						);
// D5M Control
assign	D5M_TRIGGER	=	1'b1;  // TRIGGER
assign	D5M_RESET_N	=	DLY_RST_1;	


endmodule
