D5M_VIP_QSYS |

2014.09.03.16:05:48 | Datasheet

Overview

clk_50 | D5M_VIP_QSYS

All Components
sdram altera_avalon_new_sdram_controller 13.1
Memory Map

| alt_vip_vfb_0
read_master | write_master
sdram |  |
s1 | 0x00000000 | 0x00000000

## clk_50

clock_source v13.1

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## sdram

altera_avalon_new_sdram_controller v13.1

clk_50 | clk_reset | sdram
reset
pll_sys | outclk0
clk
alt_vip_vfb_0 | read_master
s1
write_master
s1

## Parameters

TAC | 5.5
TRCD | 20.0
TRFC | 70.0
TRP | 20.0
TWR | 14.0
casLatency | 3
columnWidth | 10
dataWidth | 16
generateSimulationModel | true
initRefreshCommands | 2
model | custom
numberOfBanks | 4
numberOfChipSelects | 1
pinsSharedViaTriState | false
powerUpDelay | 100.0
refreshPeriod | 15.625
rowWidth | 13
masteredTristateBridgeSlave | 0
TMRD | 3
initNOPDelay | 0.0
registerDataIn | true
clockRate | 120000000
componentName | D5M_VIP_QSYS_sdram
size | 67108864
addressWidth | 25
bankWidth | 2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

CAS_LATENCY | 3
CONTENTS_INFO |
INIT_NOP_DELAY | 0.0
INIT_REFRESH_COMMANDS | 2
IS_INITIALIZED | 1
POWERUP_DELAY | 100.0
REFRESH_PERIOD | 15.625
REGISTER_DATA_IN | 1
SDRAM_ADDR_WIDTH | 25
SDRAM_BANK_WIDTH | 2
SDRAM_COL_WIDTH | 10
SDRAM_DATA_WIDTH | 16
SDRAM_NUM_BANKS | 4
SDRAM_NUM_CHIPSELECTS | 1
SDRAM_ROW_WIDTH | 13
SHARED_DATA | 0
SIM_MODEL_BASE | 1
STARVATION_INDICATOR | 0
TRISTATE_BRIDGE_SLAVE | ""
T_AC | 5.5
T_MRD | 3
T_RCD | 20.0
T_RFC | 70.0
T_RP | 20.0
T_WR | 14.0

## pll_sys

altera_pll v13.1

clk_50 | clk | pll_sys
refclk
clk_reset
reset
|  | outclk0 | sdram
|  | clk
|  | outclk0 | alt_vip_itc_0
|  | is_clk_rst
|  | outclk0 | d5m
|  | clock_reset
|  | outclk0 | alt_vip_vfb_0
|  | clock

## Parameters

debug_print_output | false
debug_use_rbc_taf_method | false
device_family | CYCLONEV
device | 5CSEMA5F31C6
gui_device_speed_grade | 2
gui_pll_mode | Fractional-N PLL
fractional_vco_multiplier | true
gui_reference_clock_frequency | 50.0
reference_clock_frequency | 50.0 MHz
gui_channel_spacing | 0.0
gui_operation_mode | normal
gui_feedback_clock | Global Clock
gui_fractional_cout | 32
pll_fractional_cout | 32
gui_dsm_out_sel | 1st_order
pll_dsm_out_sel | 1st_order
operation_mode | normal
gui_use_locked | true
gui_en_adv_params | false
gui_number_of_clocks | 5
number_of_clocks | 5
number_of_cascade_counters | 0
gui_multiply_factor | 1
gui_frac_multiply_factor | 1
gui_divide_factor_n | 1
gui_cascade_counter0 | false
gui_output_clock_frequency0 | 120.0
gui_divide_factor_c0 | 1
gui_actual_multiply_factor0 | 12
gui_actual_frac_multiply_factor0 | 1
gui_actual_divide_factor0 | 5
gui_actual_output_clock_frequency0 | 0 MHz
gui_ps_units0 | ps
gui_phase_shift0 | 0
gui_phase_shift_deg0 | 0.0
gui_actual_phase_shift0 | 0
gui_duty_cycle0 | 50
gui_cascade_counter1 | false
gui_output_clock_frequency1 | 120.0
gui_divide_factor_c1 | 1
gui_actual_multiply_factor1 | 12
gui_actual_frac_multiply_factor1 | 1
gui_actual_divide_factor1 | 5
gui_actual_output_clock_frequency1 | 0 MHz
gui_ps_units1 | degrees
gui_phase_shift1 | 7500
gui_phase_shift_deg1 | -90.0
gui_actual_phase_shift1 | 0
gui_duty_cycle1 | 50
gui_cascade_counter2 | false
gui_output_clock_frequency2 | 10.0
gui_divide_factor_c2 | 1
gui_actual_multiply_factor2 | 12
gui_actual_frac_multiply_factor2 | 1
gui_actual_divide_factor2 | 60
gui_actual_output_clock_frequency2 | 0 MHz
gui_ps_units2 | ps
gui_phase_shift2 | 0
gui_phase_shift_deg2 | 0.0
gui_actual_phase_shift2 | 0
gui_duty_cycle2 | 50
gui_cascade_counter3 | false
gui_output_clock_frequency3 | 25.0
gui_divide_factor_c3 | 1
gui_actual_multiply_factor3 | 12
gui_actual_frac_multiply_factor3 | 1
gui_actual_divide_factor3 | 24
gui_actual_output_clock_frequency3 | 0 MHz
gui_ps_units3 | ps
gui_phase_shift3 | 0
gui_phase_shift_deg3 | 0.0
gui_actual_phase_shift3 | 0
gui_duty_cycle3 | 50
gui_cascade_counter4 | false
gui_output_clock_frequency4 | 20.0
gui_divide_factor_c4 | 1
gui_actual_multiply_factor4 | 12
gui_actual_frac_multiply_factor4 | 1
gui_actual_divide_factor4 | 30
gui_actual_output_clock_frequency4 | 0 MHz
gui_ps_units4 | ps
gui_phase_shift4 | 0
gui_phase_shift_deg4 | 0.0
gui_actual_phase_shift4 | 0
gui_duty_cycle4 | 50
gui_cascade_counter5 | false
gui_output_clock_frequency5 | 100.0
gui_divide_factor_c5 | 1
gui_actual_multiply_factor5 | 1
gui_actual_frac_multiply_factor5 | 1
gui_actual_divide_factor5 | 1
gui_actual_output_clock_frequency5 | 0 MHz
gui_ps_units5 | ps
gui_phase_shift5 | 0
gui_phase_shift_deg5 | 0.0
gui_actual_phase_shift5 | 0
gui_duty_cycle5 | 50
gui_cascade_counter6 | false
gui_output_clock_frequency6 | 100.0
gui_divide_factor_c6 | 1
gui_actual_multiply_factor6 | 1
gui_actual_frac_multiply_factor6 | 1
gui_actual_divide_factor6 | 1
gui_actual_output_clock_frequency6 | 0 MHz
gui_ps_units6 | ps
gui_phase_shift6 | 0
gui_phase_shift_deg6 | 0.0
gui_actual_phase_shift6 | 0
gui_duty_cycle6 | 50
gui_cascade_counter7 | false
gui_output_clock_frequency7 | 100.0
gui_divide_factor_c7 | 1
gui_actual_multiply_factor7 | 1
gui_actual_frac_multiply_factor7 | 1
gui_actual_divide_factor7 | 1
gui_actual_output_clock_frequency7 | 0 MHz
gui_ps_units7 | ps
gui_phase_shift7 | 0
gui_phase_shift_deg7 | 0.0
gui_actual_phase_shift7 | 0
gui_duty_cycle7 | 50
gui_cascade_counter8 | false
gui_output_clock_frequency8 | 100.0
gui_divide_factor_c8 | 1
gui_actual_multiply_factor8 | 1
gui_actual_frac_multiply_factor8 | 1
gui_actual_divide_factor8 | 1
gui_actual_output_clock_frequency8 | 0 MHz
gui_ps_units8 | ps
gui_phase_shift8 | 0
gui_phase_shift_deg8 | 0.0
gui_actual_phase_shift8 | 0
gui_duty_cycle8 | 50
gui_cascade_counter9 | false
gui_output_clock_frequency9 | 100.0
gui_divide_factor_c9 | 1
gui_actual_multiply_factor9 | 1
gui_actual_frac_multiply_factor9 | 1
gui_actual_divide_factor9 | 1
gui_actual_output_clock_frequency9 | 0 MHz
gui_ps_units9 | ps
gui_phase_shift9 | 0
gui_phase_shift_deg9 | 0.0
gui_actual_phase_shift9 | 0
gui_duty_cycle9 | 50
gui_cascade_counter10 | false
gui_output_clock_frequency10 | 100.0
gui_divide_factor_c10 | 1
gui_actual_multiply_factor10 | 1
gui_actual_frac_multiply_factor10 | 1
gui_actual_divide_factor10 | 1
gui_actual_output_clock_frequency10 | 0 MHz
gui_ps_units10 | ps
gui_phase_shift10 | 0
gui_phase_shift_deg10 | 0.0
gui_actual_phase_shift10 | 0
gui_duty_cycle10 | 50
gui_cascade_counter11 | false
gui_output_clock_frequency11 | 100.0
gui_divide_factor_c11 | 1
gui_actual_multiply_factor11 | 1
gui_actual_frac_multiply_factor11 | 1
gui_actual_divide_factor11 | 1
gui_actual_output_clock_frequency11 | 0 MHz
gui_ps_units11 | ps
gui_phase_shift11 | 0
gui_phase_shift_deg11 | 0.0
gui_actual_phase_shift11 | 0
gui_duty_cycle11 | 50
gui_cascade_counter12 | false
gui_output_clock_frequency12 | 100.0
gui_divide_factor_c12 | 1
gui_actual_multiply_factor12 | 1
gui_actual_frac_multiply_factor12 | 1
gui_actual_divide_factor12 | 1
gui_actual_output_clock_frequency12 | 0 MHz
gui_ps_units12 | ps
gui_phase_shift12 | 0
gui_phase_shift_deg12 | 0.0
gui_actual_phase_shift12 | 0
gui_duty_cycle12 | 50
gui_cascade_counter13 | false
gui_output_clock_frequency13 | 100.0
gui_divide_factor_c13 | 1
gui_actual_multiply_factor13 | 1
gui_actual_frac_multiply_factor13 | 1
gui_actual_divide_factor13 | 1
gui_actual_output_clock_frequency13 | 0 MHz
gui_ps_units13 | ps
gui_phase_shift13 | 0
gui_phase_shift_deg13 | 0.0
gui_actual_phase_shift13 | 0
gui_duty_cycle13 | 50
gui_cascade_counter14 | false
gui_output_clock_frequency14 | 100.0
gui_divide_factor_c14 | 1
gui_actual_multiply_factor14 | 1
gui_actual_frac_multiply_factor14 | 1
gui_actual_divide_factor14 | 1
gui_actual_output_clock_frequency14 | 0 MHz
gui_ps_units14 | ps
gui_phase_shift14 | 0
gui_phase_shift_deg14 | 0.0
gui_actual_phase_shift14 | 0
gui_duty_cycle14 | 50
gui_cascade_counter15 | false
gui_output_clock_frequency15 | 100.0
gui_divide_factor_c15 | 1
gui_actual_multiply_factor15 | 1
gui_actual_frac_multiply_factor15 | 1
gui_actual_divide_factor15 | 1
gui_actual_output_clock_frequency15 | 0 MHz
gui_ps_units15 | ps
gui_phase_shift15 | 0
gui_phase_shift_deg15 | 0.0
gui_actual_phase_shift15 | 0
gui_duty_cycle15 | 50
gui_cascade_counter16 | false
gui_output_clock_frequency16 | 100.0
gui_divide_factor_c16 | 1
gui_actual_multiply_factor16 | 1
gui_actual_frac_multiply_factor16 | 1
gui_actual_divide_factor16 | 1
gui_actual_output_clock_frequency16 | 0 MHz
gui_ps_units16 | ps
gui_phase_shift16 | 0
gui_phase_shift_deg16 | 0.0
gui_actual_phase_shift16 | 0
gui_duty_cycle16 | 50
gui_cascade_counter17 | false
gui_output_clock_frequency17 | 100.0
gui_divide_factor_c17 | 1
gui_actual_multiply_factor17 | 1
gui_actual_frac_multiply_factor17 | 1
gui_actual_divide_factor17 | 1
gui_actual_output_clock_frequency17 | 0 MHz
gui_ps_units17 | ps
gui_phase_shift17 | 0
gui_phase_shift_deg17 | 0.0
gui_actual_phase_shift17 | 0
gui_duty_cycle17 | 50
output_clock_frequency0 | 120.000000 MHz
phase_shift0 | 0 ps
duty_cycle0 | 50
output_clock_frequency1 | 120.000000 MHz
phase_shift1 | 6250 ps
duty_cycle1 | 50
output_clock_frequency2 | 10.000000 MHz
phase_shift2 | 0 ps
duty_cycle2 | 50
output_clock_frequency3 | 25.000000 MHz
phase_shift3 | 0 ps
duty_cycle3 | 50
output_clock_frequency4 | 20.000000 MHz
phase_shift4 | 0 ps
duty_cycle4 | 50
output_clock_frequency5 | 0 MHz
phase_shift5 | 0 ps
duty_cycle5 | 50
output_clock_frequency6 | 0 MHz
phase_shift6 | 0 ps
duty_cycle6 | 50
output_clock_frequency7 | 0 MHz
phase_shift7 | 0 ps
duty_cycle7 | 50
output_clock_frequency8 | 0 MHz
phase_shift8 | 0 ps
duty_cycle8 | 50
output_clock_frequency9 | 0 MHz
phase_shift9 | 0 ps
duty_cycle9 | 50
output_clock_frequency10 | 0 MHz
phase_shift10 | 0 ps
duty_cycle10 | 50
output_clock_frequency11 | 0 MHz
phase_shift11 | 0 ps
duty_cycle11 | 50
output_clock_frequency12 | 0 MHz
phase_shift12 | 0 ps
duty_cycle12 | 50
output_clock_frequency13 | 0 MHz
phase_shift13 | 0 ps
duty_cycle13 | 50
output_clock_frequency14 | 0 MHz
phase_shift14 | 0 ps
duty_cycle14 | 50
output_clock_frequency15 | 0 MHz
phase_shift15 | 0 ps
duty_cycle15 | 50
output_clock_frequency16 | 0 MHz
phase_shift16 | 0 ps
duty_cycle16 | 50
output_clock_frequency17 | 0 MHz
phase_shift17 | 0 ps
duty_cycle17 | 50
gui_pll_auto_reset | Off
gui_pll_bandwidth_preset | Auto
gui_en_reconf | false
gui_en_dps_ports | false
gui_en_phout_ports | false
gui_phout_division | 1
gui_en_lvds_ports | false
pll_vcoph_div | 1
pll_type | General
pll_subtype | General
m_cnt_hi_div | 6
m_cnt_lo_div | 6
n_cnt_hi_div | 256
n_cnt_lo_div | 256
m_cnt_bypass_en | false
n_cnt_bypass_en | true
m_cnt_odd_div_duty_en | false
n_cnt_odd_div_duty_en | false
c_cnt_hi_div0 | 3
c_cnt_lo_div0 | 2
c_cnt_prst0 | 1
c_cnt_ph_mux_prst0 | 0
c_cnt_in_src0 | ph_mux_clk
c_cnt_bypass_en0 | false
c_cnt_odd_div_duty_en0 | true
c_cnt_hi_div1 | 3
c_cnt_lo_div1 | 2
c_cnt_prst1 | 4
c_cnt_ph_mux_prst1 | 6
c_cnt_in_src1 | ph_mux_clk
c_cnt_bypass_en1 | false
c_cnt_odd_div_duty_en1 | true
c_cnt_hi_div2 | 30
c_cnt_lo_div2 | 30
c_cnt_prst2 | 1
c_cnt_ph_mux_prst2 | 0
c_cnt_in_src2 | ph_mux_clk
c_cnt_bypass_en2 | false
c_cnt_odd_div_duty_en2 | false
c_cnt_hi_div3 | 12
c_cnt_lo_div3 | 12
c_cnt_prst3 | 1
c_cnt_ph_mux_prst3 | 0
c_cnt_in_src3 | ph_mux_clk
c_cnt_bypass_en3 | false
c_cnt_odd_div_duty_en3 | false
c_cnt_hi_div4 | 15
c_cnt_lo_div4 | 15
c_cnt_prst4 | 1
c_cnt_ph_mux_prst4 | 0
c_cnt_in_src4 | ph_mux_clk
c_cnt_bypass_en4 | false
c_cnt_odd_div_duty_en4 | false
c_cnt_hi_div5 | 1
c_cnt_lo_div5 | 1
c_cnt_prst5 | 1
c_cnt_ph_mux_prst5 | 0
c_cnt_in_src5 | ph_mux_clk
c_cnt_bypass_en5 | true
c_cnt_odd_div_duty_en5 | false
c_cnt_hi_div6 | 1
c_cnt_lo_div6 | 1
c_cnt_prst6 | 1
c_cnt_ph_mux_prst6 | 0
c_cnt_in_src6 | ph_mux_clk
c_cnt_bypass_en6 | true
c_cnt_odd_div_duty_en6 | false
c_cnt_hi_div7 | 1
c_cnt_lo_div7 | 1
c_cnt_prst7 | 1
c_cnt_ph_mux_prst7 | 0
c_cnt_in_src7 | ph_mux_clk
c_cnt_bypass_en7 | true
c_cnt_odd_div_duty_en7 | false
c_cnt_hi_div8 | 1
c_cnt_lo_div8 | 1
c_cnt_prst8 | 1
c_cnt_ph_mux_prst8 | 0
c_cnt_in_src8 | ph_mux_clk
c_cnt_bypass_en8 | true
c_cnt_odd_div_duty_en8 | false
c_cnt_hi_div9 | 1
c_cnt_lo_div9 | 1
c_cnt_prst9 | 1
c_cnt_ph_mux_prst9 | 0
c_cnt_in_src9 | ph_mux_clk
c_cnt_bypass_en9 | true
c_cnt_odd_div_duty_en9 | false
c_cnt_hi_div10 | 1
c_cnt_lo_div10 | 1
c_cnt_prst10 | 1
c_cnt_ph_mux_prst10 | 0
c_cnt_in_src10 | ph_mux_clk
c_cnt_bypass_en10 | true
c_cnt_odd_div_duty_en10 | false
c_cnt_hi_div11 | 1
c_cnt_lo_div11 | 1
c_cnt_prst11 | 1
c_cnt_ph_mux_prst11 | 0
c_cnt_in_src11 | ph_mux_clk
c_cnt_bypass_en11 | true
c_cnt_odd_div_duty_en11 | false
c_cnt_hi_div12 | 1
c_cnt_lo_div12 | 1
c_cnt_prst12 | 1
c_cnt_ph_mux_prst12 | 0
c_cnt_in_src12 | ph_mux_clk
c_cnt_bypass_en12 | true
c_cnt_odd_div_duty_en12 | false
c_cnt_hi_div13 | 1
c_cnt_lo_div13 | 1
c_cnt_prst13 | 1
c_cnt_ph_mux_prst13 | 0
c_cnt_in_src13 | ph_mux_clk
c_cnt_bypass_en13 | true
c_cnt_odd_div_duty_en13 | false
c_cnt_hi_div14 | 1
c_cnt_lo_div14 | 1
c_cnt_prst14 | 1
c_cnt_ph_mux_prst14 | 0
c_cnt_in_src14 | ph_mux_clk
c_cnt_bypass_en14 | true
c_cnt_odd_div_duty_en14 | false
c_cnt_hi_div15 | 1
c_cnt_lo_div15 | 1
c_cnt_prst15 | 1
c_cnt_ph_mux_prst15 | 0
c_cnt_in_src15 | ph_mux_clk
c_cnt_bypass_en15 | true
c_cnt_odd_div_duty_en15 | false
c_cnt_hi_div16 | 1
c_cnt_lo_div16 | 1
c_cnt_prst16 | 1
c_cnt_ph_mux_prst16 | 0
c_cnt_in_src16 | ph_mux_clk
c_cnt_bypass_en16 | true
c_cnt_odd_div_duty_en16 | false
c_cnt_hi_div17 | 1
c_cnt_lo_div17 | 1
c_cnt_prst17 | 1
c_cnt_ph_mux_prst17 | 0
c_cnt_in_src17 | ph_mux_clk
c_cnt_bypass_en17 | true
c_cnt_odd_div_duty_en17 | false
pll_vco_div | 1
pll_cp_current | 30
pll_bwctrl | 2000
pll_output_clk_frequency | 600.0 MHz
pll_fractional_division | 1
mimic_fbclk_type | gclk
pll_fbclk_mux_1 | glb
pll_fbclk_mux_2 | fb_1
pll_m_cnt_in_src | ph_mux_clk
gui_parameter_list | M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX
gui_parameter_values | 6,6,256,256,false,true,false,false,3,2,1,0,ph_mux_clk,false,true,3,2,4,6,ph_mux_clk,false,true,30,30,1,0,ph_mux_clk,false,false,12,12,1,0,ph_mux_clk,false,false,15,15,1,0,ph_mux_clk,false,false,1,30,2000,600.0 MHz,1,gclk,glb,fb_1,ph_mux_clk
gui_mif_generate | false
gui_enable_mif_dps | false
gui_dps_cntr | C0
gui_dps_num | 1
gui_dps_dir | Positive
gui_refclk_switch | false
gui_refclk1_frequency | 100.0
gui_switchover_mode | Automatic Switchover
gui_switchover_delay | 0
gui_active_clk | false
gui_clk_bad | false
refclk1_frequency | 100.0 MHz
pll_clk_loss_sw_en | false
pll_manu_clk_sw_en | false
pll_auto_clk_sw_en | false
pll_clkin_1_src | clk_0
pll_clk_sw_dly | 0
gui_enable_cascade_out | false
gui_cascade_outclk_index | 0
gui_enable_cascade_in | false
pll_clkin_0_src | clk_0
gui_pll_cascading_mode | Create an adjpllin signal to connect with an upstream PLL
AUTO_REFCLK_CLOCK_RATE | 50000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_vip_itc_0

alt_vip_itc v13.1

pll_sys | outclk0 | alt_vip_itc_0
is_clk_rst
clk_50 | clk_reset
is_clk_rst_reset
alt_vip_vfb_0 | dout
din

## Parameters

FAMILY | CYCLONEV
NUMBER_OF_COLOUR_PLANES | 3
COLOUR_PLANES_ARE_IN_PARALLEL | 1
BPS | 8
INTERLACED | 0
H_ACTIVE_PIXELS | 640
V_ACTIVE_LINES | 480
ACCEPT_COLOURS_IN_SEQ | 0
FIFO_DEPTH | 6399
CLOCKS_ARE_SAME | 0
USE_CONTROL | 0
NO_OF_MODES | 1
THRESHOLD | 4799
STD_WIDTH | 1
GENERATE_SYNC | 0
USE_EMBEDDED_SYNCS | 0
AP_LINE | 0
V_BLANK | 0
H_BLANK | 0
H_SYNC_LENGTH | 96
H_FRONT_PORCH | 16
H_BACK_PORCH | 49
V_SYNC_LENGTH | 2
V_FRONT_PORCH | 10
V_BACK_PORCH | 33
F_RISING_EDGE | 0
F_FALLING_EDGE | 0
FIELD0_V_RISING_EDGE | 0
FIELD0_V_BLANK | 0
FIELD0_V_SYNC_LENGTH | 0
FIELD0_V_FRONT_PORCH | 0
FIELD0_V_BACK_PORCH | 0
ANC_LINE | 0
FIELD0_ANC_LINE | 0
AUTO_IS_CLK_RST_CLOCK_RATE | 120000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## d5m

TERASIC_CAMERA v1.0

pll_sys | outclk0 | d5m
clock_reset
clk_50 | clk_reset
clock_reset_reset
|  | avalon_streaming_source | alt_vip_vfb_0
|  | din

## Parameters

VIDEO_W | 640
VIDEO_H | 480
AUTO_CLOCK_RESET_CLOCK_RATE | 120000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_vip_vfb_0

alt_vip_vfb v13.1

d5m | avalon_streaming_source | alt_vip_vfb_0
din
pll_sys | outclk0
clock
clk_50 | clk_reset
reset
|  | dout | alt_vip_itc_0
|  | din
|  | read_master | sdram
|  | s1
|  | write_master
|  | s1

## Parameters

AUTO_DEVICE_FAMILY | CYCLONEV
AUTO_READ_MASTER_INTERRUPT_USED_MASK | 0
AUTO_WRITE_MASTER_MAX_READ_LATENCY | 2
AUTO_WRITE_MASTER_INTERRUPT_USED_MASK | 0
AUTO_WRITE_MASTER_CLOCKS_SAME | 2
AUTO_READ_MASTER_MAX_READ_LATENCY | 2
AUTO_WRITE_MASTER_NEED_ADDR_WIDTH | 27
AUTO_READ_MASTER_NEED_ADDR_WIDTH | 27
AUTO_WRITER_CONTROL_CLOCKS_SAME | 0
AUTO_READ_MASTER_CLOCKS_SAME | 2
AUTO_READER_CONTROL_CLOCKS_SAME | 0
PARAMETERISATION | <frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>640</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>480</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>0</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>1</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>1</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>00000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>32</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>0</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>256</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>32</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>256</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>32</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>0</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>0</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>0</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>true</VFB_DROP_INVALID_FIELDS></frameBufferParams>
deviceFamily | Cyclone V
generateLegacySim | false

## Software Assignments

(none)

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