# TCL File Generated by Component Editor 12.0
# Wed Jun 27 10:19:43 CST 2012
# DO NOT MODIFY


# 
# TERASIC_CLOCK_COUNT "TERASIC_CLOCK_COUNT" v1.0
# null 2012.06.27.10:19:43
# 
# 

# 
# request TCL package from ACDS 12.0
# 
package require -exact qsys 12.0


# 
# module TERASIC_CLOCK_COUNT
# 
set_module_property NAME TERASIC_CLOCK_COUNT
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Terasic Qsys Component/"
set_module_property DISPLAY_NAME TERASIC_CLOCK_COUNT
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false


# 
# file sets
# 
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL TERASIC_CLOCK_COUNT
set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file TERASIC_CLOCK_COUNT.v VERILOG PATH TERASIC_CLOCK_COUNT.v
add_fileset_file CLOCK_COUNTER.v VERILOG PATH CLOCK_COUNTER.v

add_fileset sim_verilog SIM_VERILOG "" "Verilog Simulation"
set_fileset_property sim_verilog TOP_LEVEL TERASIC_CLOCK_COUNT
set_fileset_property sim_verilog ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file TERASIC_CLOCK_COUNT.v VERILOG PATH TERASIC_CLOCK_COUNT.v
add_fileset_file CLOCK_COUNTER.v VERILOG PATH CLOCK_COUNTER.v


# 
# parameters
# 


# 
# display items
# 


# 
# connection point clk
# 
add_interface clk clock end
set_interface_property clk clockRate 0
set_interface_property clk ENABLED true

add_interface_port clk s_clk_in clk Input 1


# 
# connection point Slave
# 
add_interface Slave avalon end
set_interface_property Slave addressAlignment DYNAMIC
set_interface_property Slave addressUnits WORDS
set_interface_property Slave associatedClock clk
set_interface_property Slave associatedReset reset
set_interface_property Slave burstOnBurstBoundariesOnly false
set_interface_property Slave explicitAddressSpan 0
set_interface_property Slave holdTime 0
set_interface_property Slave isMemoryDevice false
set_interface_property Slave isNonVolatileStorage false
set_interface_property Slave linewrapBursts false
set_interface_property Slave maximumPendingReadTransactions 0
set_interface_property Slave printableDevice false
set_interface_property Slave readLatency 0
set_interface_property Slave readWaitTime 1
set_interface_property Slave setupTime 0
set_interface_property Slave timingUnits Cycles
set_interface_property Slave writeWaitTime 0
set_interface_property Slave ENABLED true

add_interface_port Slave s_address_in address Input 2
add_interface_port Slave s_read_in read Input 1
add_interface_port Slave s_readdata_out readdata Output 32
add_interface_port Slave s_write_in write Input 1
add_interface_port Slave s_writedata_in writedata Input 32


# 
# connection point clk_in_ref
# 
add_interface clk_in_ref conduit end
set_interface_property clk_in_ref associatedClock ""
set_interface_property clk_in_ref associatedReset ""
set_interface_property clk_in_ref ENABLED true

add_interface_port clk_in_ref CLK_1 export Input 1


# 
# connection point clk_in_target
# 
add_interface clk_in_target conduit end
set_interface_property clk_in_target associatedClock ""
set_interface_property clk_in_target associatedReset ""
set_interface_property clk_in_target ENABLED true

add_interface_port clk_in_target CLK_2 export Input 1


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock clk
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true

add_interface_port reset s_reset_in reset Input 1

