// DE1_SoC_QSYS_mm_interconnect_1.v

// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 13.1 162 at 2013.12.01.17:38:25

`timescale 1 ps / 1 ps
module DE1_SoC_QSYS_mm_interconnect_1 (
		output wire [7:0]   hps_0_f2h_axi_slave_awid,                                         //                                        hps_0_f2h_axi_slave.awid
		output wire [31:0]  hps_0_f2h_axi_slave_awaddr,                                       //                                                           .awaddr
		output wire [3:0]   hps_0_f2h_axi_slave_awlen,                                        //                                                           .awlen
		output wire [2:0]   hps_0_f2h_axi_slave_awsize,                                       //                                                           .awsize
		output wire [1:0]   hps_0_f2h_axi_slave_awburst,                                      //                                                           .awburst
		output wire [1:0]   hps_0_f2h_axi_slave_awlock,                                       //                                                           .awlock
		output wire [3:0]   hps_0_f2h_axi_slave_awcache,                                      //                                                           .awcache
		output wire [2:0]   hps_0_f2h_axi_slave_awprot,                                       //                                                           .awprot
		output wire [4:0]   hps_0_f2h_axi_slave_awuser,                                       //                                                           .awuser
		output wire         hps_0_f2h_axi_slave_awvalid,                                      //                                                           .awvalid
		input  wire         hps_0_f2h_axi_slave_awready,                                      //                                                           .awready
		output wire [7:0]   hps_0_f2h_axi_slave_wid,                                          //                                                           .wid
		output wire [127:0] hps_0_f2h_axi_slave_wdata,                                        //                                                           .wdata
		output wire [15:0]  hps_0_f2h_axi_slave_wstrb,                                        //                                                           .wstrb
		output wire         hps_0_f2h_axi_slave_wlast,                                        //                                                           .wlast
		output wire         hps_0_f2h_axi_slave_wvalid,                                       //                                                           .wvalid
		input  wire         hps_0_f2h_axi_slave_wready,                                       //                                                           .wready
		input  wire [7:0]   hps_0_f2h_axi_slave_bid,                                          //                                                           .bid
		input  wire [1:0]   hps_0_f2h_axi_slave_bresp,                                        //                                                           .bresp
		input  wire         hps_0_f2h_axi_slave_bvalid,                                       //                                                           .bvalid
		output wire         hps_0_f2h_axi_slave_bready,                                       //                                                           .bready
		output wire [7:0]   hps_0_f2h_axi_slave_arid,                                         //                                                           .arid
		output wire [31:0]  hps_0_f2h_axi_slave_araddr,                                       //                                                           .araddr
		output wire [3:0]   hps_0_f2h_axi_slave_arlen,                                        //                                                           .arlen
		output wire [2:0]   hps_0_f2h_axi_slave_arsize,                                       //                                                           .arsize
		output wire [1:0]   hps_0_f2h_axi_slave_arburst,                                      //                                                           .arburst
		output wire [1:0]   hps_0_f2h_axi_slave_arlock,                                       //                                                           .arlock
		output wire [3:0]   hps_0_f2h_axi_slave_arcache,                                      //                                                           .arcache
		output wire [2:0]   hps_0_f2h_axi_slave_arprot,                                       //                                                           .arprot
		output wire [4:0]   hps_0_f2h_axi_slave_aruser,                                       //                                                           .aruser
		output wire         hps_0_f2h_axi_slave_arvalid,                                      //                                                           .arvalid
		input  wire         hps_0_f2h_axi_slave_arready,                                      //                                                           .arready
		input  wire [7:0]   hps_0_f2h_axi_slave_rid,                                          //                                                           .rid
		input  wire [127:0] hps_0_f2h_axi_slave_rdata,                                        //                                                           .rdata
		input  wire [1:0]   hps_0_f2h_axi_slave_rresp,                                        //                                                           .rresp
		input  wire         hps_0_f2h_axi_slave_rlast,                                        //                                                           .rlast
		input  wire         hps_0_f2h_axi_slave_rvalid,                                       //                                                           .rvalid
		output wire         hps_0_f2h_axi_slave_rready,                                       //                                                           .rready
		input  wire         clk_50_clk_clk,                                                   //                                                 clk_50_clk.clk
		input  wire         pll_sys_outclk0_clk,                                              //                                            pll_sys_outclk0.clk
		input  wire         alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset,     //     alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset.reset
		input  wire         hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset, // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
		input  wire [31:0]  alt_vip_vfr_0_avalon_master_address,                              //                                alt_vip_vfr_0_avalon_master.address
		output wire         alt_vip_vfr_0_avalon_master_waitrequest,                          //                                                           .waitrequest
		input  wire [1:0]   alt_vip_vfr_0_avalon_master_burstcount,                           //                                                           .burstcount
		input  wire         alt_vip_vfr_0_avalon_master_read,                                 //                                                           .read
		output wire [255:0] alt_vip_vfr_0_avalon_master_readdata,                             //                                                           .readdata
		output wire         alt_vip_vfr_0_avalon_master_readdatavalid                         //                                                           .readdatavalid
	);

	wire          alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_waitrequest;            // alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_waitrequest -> alt_vip_vfr_0_avalon_master_translator:uav_waitrequest
	wire    [6:0] alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_burstcount;             // alt_vip_vfr_0_avalon_master_translator:uav_burstcount -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire  [255:0] alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_writedata;              // alt_vip_vfr_0_avalon_master_translator:uav_writedata -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_address;                // alt_vip_vfr_0_avalon_master_translator:uav_address -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_address
	wire          alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_lock;                   // alt_vip_vfr_0_avalon_master_translator:uav_lock -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_lock
	wire          alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_write;                  // alt_vip_vfr_0_avalon_master_translator:uav_write -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_write
	wire          alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_read;                   // alt_vip_vfr_0_avalon_master_translator:uav_read -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_read
	wire  [255:0] alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_readdata;               // alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdata -> alt_vip_vfr_0_avalon_master_translator:uav_readdata
	wire          alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_debugaccess;            // alt_vip_vfr_0_avalon_master_translator:uav_debugaccess -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire   [31:0] alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_byteenable;             // alt_vip_vfr_0_avalon_master_translator:uav_byteenable -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire          alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_readdatavalid;          // alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> alt_vip_vfr_0_avalon_master_translator:uav_readdatavalid
	wire          alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket;   // alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
	wire          alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid;         // alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
	wire          alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
	wire  [371:0] alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data;          // alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
	wire          alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready;         // addr_router:sink_ready -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:cp_ready
	wire          addr_router_src_endofpacket;                                                             // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
	wire          addr_router_src_valid;                                                                   // addr_router:src_valid -> limiter:cmd_sink_valid
	wire          addr_router_src_startofpacket;                                                           // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
	wire  [371:0] addr_router_src_data;                                                                    // addr_router:src_data -> limiter:cmd_sink_data
	wire    [1:0] addr_router_src_channel;                                                                 // addr_router:src_channel -> limiter:cmd_sink_channel
	wire          addr_router_src_ready;                                                                   // limiter:cmd_sink_ready -> addr_router:src_ready
	wire          limiter_rsp_src_endofpacket;                                                             // limiter:rsp_src_endofpacket -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          limiter_rsp_src_valid;                                                                   // limiter:rsp_src_valid -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:rp_valid
	wire          limiter_rsp_src_startofpacket;                                                           // limiter:rsp_src_startofpacket -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [371:0] limiter_rsp_src_data;                                                                    // limiter:rsp_src_data -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:rp_data
	wire    [1:0] limiter_rsp_src_channel;                                                                 // limiter:rsp_src_channel -> alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:rp_channel
	wire          limiter_rsp_src_ready;                                                                   // alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
	wire          cmd_xbar_mux_src_endofpacket;                                                            // cmd_xbar_mux:src_endofpacket -> width_adapter:in_endofpacket
	wire          cmd_xbar_mux_src_valid;                                                                  // cmd_xbar_mux:src_valid -> width_adapter:in_valid
	wire          cmd_xbar_mux_src_startofpacket;                                                          // cmd_xbar_mux:src_startofpacket -> width_adapter:in_startofpacket
	wire  [371:0] cmd_xbar_mux_src_data;                                                                   // cmd_xbar_mux:src_data -> width_adapter:in_data
	wire    [1:0] cmd_xbar_mux_src_channel;                                                                // cmd_xbar_mux:src_channel -> width_adapter:in_channel
	wire          cmd_xbar_mux_src_ready;                                                                  // width_adapter:in_ready -> cmd_xbar_mux:src_ready
	wire          cmd_xbar_mux_001_src_endofpacket;                                                        // cmd_xbar_mux_001:src_endofpacket -> width_adapter_001:in_endofpacket
	wire          cmd_xbar_mux_001_src_valid;                                                              // cmd_xbar_mux_001:src_valid -> width_adapter_001:in_valid
	wire          cmd_xbar_mux_001_src_startofpacket;                                                      // cmd_xbar_mux_001:src_startofpacket -> width_adapter_001:in_startofpacket
	wire  [371:0] cmd_xbar_mux_001_src_data;                                                               // cmd_xbar_mux_001:src_data -> width_adapter_001:in_data
	wire    [1:0] cmd_xbar_mux_001_src_channel;                                                            // cmd_xbar_mux_001:src_channel -> width_adapter_001:in_channel
	wire          cmd_xbar_mux_001_src_ready;                                                              // width_adapter_001:in_ready -> cmd_xbar_mux_001:src_ready
	wire          id_router_src_endofpacket;                                                               // id_router:src_endofpacket -> width_adapter_002:in_endofpacket
	wire          id_router_src_valid;                                                                     // id_router:src_valid -> width_adapter_002:in_valid
	wire          id_router_src_startofpacket;                                                             // id_router:src_startofpacket -> width_adapter_002:in_startofpacket
	wire  [227:0] id_router_src_data;                                                                      // id_router:src_data -> width_adapter_002:in_data
	wire    [1:0] id_router_src_channel;                                                                   // id_router:src_channel -> width_adapter_002:in_channel
	wire          id_router_src_ready;                                                                     // width_adapter_002:in_ready -> id_router:src_ready
	wire          width_adapter_002_src_endofpacket;                                                       // width_adapter_002:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
	wire          width_adapter_002_src_valid;                                                             // width_adapter_002:out_valid -> rsp_xbar_demux:sink_valid
	wire          width_adapter_002_src_startofpacket;                                                     // width_adapter_002:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
	wire  [371:0] width_adapter_002_src_data;                                                              // width_adapter_002:out_data -> rsp_xbar_demux:sink_data
	wire          width_adapter_002_src_ready;                                                             // rsp_xbar_demux:sink_ready -> width_adapter_002:out_ready
	wire    [1:0] width_adapter_002_src_channel;                                                           // width_adapter_002:out_channel -> rsp_xbar_demux:sink_channel
	wire          id_router_001_src_endofpacket;                                                           // id_router_001:src_endofpacket -> width_adapter_003:in_endofpacket
	wire          id_router_001_src_valid;                                                                 // id_router_001:src_valid -> width_adapter_003:in_valid
	wire          id_router_001_src_startofpacket;                                                         // id_router_001:src_startofpacket -> width_adapter_003:in_startofpacket
	wire  [227:0] id_router_001_src_data;                                                                  // id_router_001:src_data -> width_adapter_003:in_data
	wire    [1:0] id_router_001_src_channel;                                                               // id_router_001:src_channel -> width_adapter_003:in_channel
	wire          id_router_001_src_ready;                                                                 // width_adapter_003:in_ready -> id_router_001:src_ready
	wire          width_adapter_003_src_endofpacket;                                                       // width_adapter_003:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
	wire          width_adapter_003_src_valid;                                                             // width_adapter_003:out_valid -> rsp_xbar_demux_001:sink_valid
	wire          width_adapter_003_src_startofpacket;                                                     // width_adapter_003:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
	wire  [371:0] width_adapter_003_src_data;                                                              // width_adapter_003:out_data -> rsp_xbar_demux_001:sink_data
	wire          width_adapter_003_src_ready;                                                             // rsp_xbar_demux_001:sink_ready -> width_adapter_003:out_ready
	wire    [1:0] width_adapter_003_src_channel;                                                           // width_adapter_003:out_channel -> rsp_xbar_demux_001:sink_channel
	wire          cmd_xbar_demux_src0_endofpacket;                                                         // cmd_xbar_demux:src0_endofpacket -> crosser:in_endofpacket
	wire          cmd_xbar_demux_src0_valid;                                                               // cmd_xbar_demux:src0_valid -> crosser:in_valid
	wire          cmd_xbar_demux_src0_startofpacket;                                                       // cmd_xbar_demux:src0_startofpacket -> crosser:in_startofpacket
	wire  [371:0] cmd_xbar_demux_src0_data;                                                                // cmd_xbar_demux:src0_data -> crosser:in_data
	wire    [1:0] cmd_xbar_demux_src0_channel;                                                             // cmd_xbar_demux:src0_channel -> crosser:in_channel
	wire          cmd_xbar_demux_src0_ready;                                                               // crosser:in_ready -> cmd_xbar_demux:src0_ready
	wire          crosser_out_endofpacket;                                                                 // crosser:out_endofpacket -> cmd_xbar_mux:sink0_endofpacket
	wire          crosser_out_valid;                                                                       // crosser:out_valid -> cmd_xbar_mux:sink0_valid
	wire          crosser_out_startofpacket;                                                               // crosser:out_startofpacket -> cmd_xbar_mux:sink0_startofpacket
	wire  [371:0] crosser_out_data;                                                                        // crosser:out_data -> cmd_xbar_mux:sink0_data
	wire    [1:0] crosser_out_channel;                                                                     // crosser:out_channel -> cmd_xbar_mux:sink0_channel
	wire          crosser_out_ready;                                                                       // cmd_xbar_mux:sink0_ready -> crosser:out_ready
	wire          cmd_xbar_demux_src1_endofpacket;                                                         // cmd_xbar_demux:src1_endofpacket -> crosser_001:in_endofpacket
	wire          cmd_xbar_demux_src1_valid;                                                               // cmd_xbar_demux:src1_valid -> crosser_001:in_valid
	wire          cmd_xbar_demux_src1_startofpacket;                                                       // cmd_xbar_demux:src1_startofpacket -> crosser_001:in_startofpacket
	wire  [371:0] cmd_xbar_demux_src1_data;                                                                // cmd_xbar_demux:src1_data -> crosser_001:in_data
	wire    [1:0] cmd_xbar_demux_src1_channel;                                                             // cmd_xbar_demux:src1_channel -> crosser_001:in_channel
	wire          cmd_xbar_demux_src1_ready;                                                               // crosser_001:in_ready -> cmd_xbar_demux:src1_ready
	wire          crosser_001_out_endofpacket;                                                             // crosser_001:out_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
	wire          crosser_001_out_valid;                                                                   // crosser_001:out_valid -> cmd_xbar_mux_001:sink0_valid
	wire          crosser_001_out_startofpacket;                                                           // crosser_001:out_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
	wire  [371:0] crosser_001_out_data;                                                                    // crosser_001:out_data -> cmd_xbar_mux_001:sink0_data
	wire    [1:0] crosser_001_out_channel;                                                                 // crosser_001:out_channel -> cmd_xbar_mux_001:sink0_channel
	wire          crosser_001_out_ready;                                                                   // cmd_xbar_mux_001:sink0_ready -> crosser_001:out_ready
	wire          rsp_xbar_demux_src0_endofpacket;                                                         // rsp_xbar_demux:src0_endofpacket -> crosser_002:in_endofpacket
	wire          rsp_xbar_demux_src0_valid;                                                               // rsp_xbar_demux:src0_valid -> crosser_002:in_valid
	wire          rsp_xbar_demux_src0_startofpacket;                                                       // rsp_xbar_demux:src0_startofpacket -> crosser_002:in_startofpacket
	wire  [371:0] rsp_xbar_demux_src0_data;                                                                // rsp_xbar_demux:src0_data -> crosser_002:in_data
	wire    [1:0] rsp_xbar_demux_src0_channel;                                                             // rsp_xbar_demux:src0_channel -> crosser_002:in_channel
	wire          rsp_xbar_demux_src0_ready;                                                               // crosser_002:in_ready -> rsp_xbar_demux:src0_ready
	wire          crosser_002_out_endofpacket;                                                             // crosser_002:out_endofpacket -> rsp_xbar_mux:sink0_endofpacket
	wire          crosser_002_out_valid;                                                                   // crosser_002:out_valid -> rsp_xbar_mux:sink0_valid
	wire          crosser_002_out_startofpacket;                                                           // crosser_002:out_startofpacket -> rsp_xbar_mux:sink0_startofpacket
	wire  [371:0] crosser_002_out_data;                                                                    // crosser_002:out_data -> rsp_xbar_mux:sink0_data
	wire    [1:0] crosser_002_out_channel;                                                                 // crosser_002:out_channel -> rsp_xbar_mux:sink0_channel
	wire          crosser_002_out_ready;                                                                   // rsp_xbar_mux:sink0_ready -> crosser_002:out_ready
	wire          rsp_xbar_demux_001_src0_endofpacket;                                                     // rsp_xbar_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
	wire          rsp_xbar_demux_001_src0_valid;                                                           // rsp_xbar_demux_001:src0_valid -> crosser_003:in_valid
	wire          rsp_xbar_demux_001_src0_startofpacket;                                                   // rsp_xbar_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
	wire  [371:0] rsp_xbar_demux_001_src0_data;                                                            // rsp_xbar_demux_001:src0_data -> crosser_003:in_data
	wire    [1:0] rsp_xbar_demux_001_src0_channel;                                                         // rsp_xbar_demux_001:src0_channel -> crosser_003:in_channel
	wire          rsp_xbar_demux_001_src0_ready;                                                           // crosser_003:in_ready -> rsp_xbar_demux_001:src0_ready
	wire          crosser_003_out_endofpacket;                                                             // crosser_003:out_endofpacket -> rsp_xbar_mux:sink1_endofpacket
	wire          crosser_003_out_valid;                                                                   // crosser_003:out_valid -> rsp_xbar_mux:sink1_valid
	wire          crosser_003_out_startofpacket;                                                           // crosser_003:out_startofpacket -> rsp_xbar_mux:sink1_startofpacket
	wire  [371:0] crosser_003_out_data;                                                                    // crosser_003:out_data -> rsp_xbar_mux:sink1_data
	wire    [1:0] crosser_003_out_channel;                                                                 // crosser_003:out_channel -> rsp_xbar_mux:sink1_channel
	wire          crosser_003_out_ready;                                                                   // rsp_xbar_mux:sink1_ready -> crosser_003:out_ready
	wire          limiter_cmd_src_endofpacket;                                                             // limiter:cmd_src_endofpacket -> limiter_pipeline:in_endofpacket
	wire    [0:0] limiter_cmd_src_valid;                                                                   // limiter:cmd_src_valid -> limiter_pipeline:in_valid
	wire          limiter_cmd_src_startofpacket;                                                           // limiter:cmd_src_startofpacket -> limiter_pipeline:in_startofpacket
	wire  [371:0] limiter_cmd_src_data;                                                                    // limiter:cmd_src_data -> limiter_pipeline:in_data
	wire    [1:0] limiter_cmd_src_channel;                                                                 // limiter:cmd_src_channel -> limiter_pipeline:in_channel
	wire          limiter_cmd_src_ready;                                                                   // limiter_pipeline:in_ready -> limiter:cmd_src_ready
	wire          limiter_pipeline_source0_endofpacket;                                                    // limiter_pipeline:out_endofpacket -> cmd_xbar_demux:sink_endofpacket
	wire          limiter_pipeline_source0_valid;                                                          // limiter_pipeline:out_valid -> cmd_xbar_demux:sink_valid
	wire          limiter_pipeline_source0_startofpacket;                                                  // limiter_pipeline:out_startofpacket -> cmd_xbar_demux:sink_startofpacket
	wire  [371:0] limiter_pipeline_source0_data;                                                           // limiter_pipeline:out_data -> cmd_xbar_demux:sink_data
	wire    [1:0] limiter_pipeline_source0_channel;                                                        // limiter_pipeline:out_channel -> cmd_xbar_demux:sink_channel
	wire          limiter_pipeline_source0_ready;                                                          // cmd_xbar_demux:sink_ready -> limiter_pipeline:out_ready
	wire          rsp_xbar_mux_src_endofpacket;                                                            // rsp_xbar_mux:src_endofpacket -> limiter_pipeline_001:in_endofpacket
	wire          rsp_xbar_mux_src_valid;                                                                  // rsp_xbar_mux:src_valid -> limiter_pipeline_001:in_valid
	wire          rsp_xbar_mux_src_startofpacket;                                                          // rsp_xbar_mux:src_startofpacket -> limiter_pipeline_001:in_startofpacket
	wire  [371:0] rsp_xbar_mux_src_data;                                                                   // rsp_xbar_mux:src_data -> limiter_pipeline_001:in_data
	wire    [1:0] rsp_xbar_mux_src_channel;                                                                // rsp_xbar_mux:src_channel -> limiter_pipeline_001:in_channel
	wire          rsp_xbar_mux_src_ready;                                                                  // limiter_pipeline_001:in_ready -> rsp_xbar_mux:src_ready
	wire          limiter_pipeline_001_source0_endofpacket;                                                // limiter_pipeline_001:out_endofpacket -> limiter:rsp_sink_endofpacket
	wire          limiter_pipeline_001_source0_valid;                                                      // limiter_pipeline_001:out_valid -> limiter:rsp_sink_valid
	wire          limiter_pipeline_001_source0_startofpacket;                                              // limiter_pipeline_001:out_startofpacket -> limiter:rsp_sink_startofpacket
	wire  [371:0] limiter_pipeline_001_source0_data;                                                       // limiter_pipeline_001:out_data -> limiter:rsp_sink_data
	wire    [1:0] limiter_pipeline_001_source0_channel;                                                    // limiter_pipeline_001:out_channel -> limiter:rsp_sink_channel
	wire          limiter_pipeline_001_source0_ready;                                                      // limiter:rsp_sink_ready -> limiter_pipeline_001:out_ready
	wire          width_adapter_src_endofpacket;                                                           // width_adapter:out_endofpacket -> agent_pipeline:in_endofpacket
	wire          width_adapter_src_valid;                                                                 // width_adapter:out_valid -> agent_pipeline:in_valid
	wire          width_adapter_src_startofpacket;                                                         // width_adapter:out_startofpacket -> agent_pipeline:in_startofpacket
	wire  [227:0] width_adapter_src_data;                                                                  // width_adapter:out_data -> agent_pipeline:in_data
	wire          width_adapter_src_ready;                                                                 // agent_pipeline:in_ready -> width_adapter:out_ready
	wire    [1:0] width_adapter_src_channel;                                                               // width_adapter:out_channel -> agent_pipeline:in_channel
	wire          agent_pipeline_source0_endofpacket;                                                      // agent_pipeline:out_endofpacket -> hps_0_f2h_axi_slave_agent:write_cp_endofpacket
	wire          agent_pipeline_source0_valid;                                                            // agent_pipeline:out_valid -> hps_0_f2h_axi_slave_agent:write_cp_valid
	wire          agent_pipeline_source0_startofpacket;                                                    // agent_pipeline:out_startofpacket -> hps_0_f2h_axi_slave_agent:write_cp_startofpacket
	wire  [227:0] agent_pipeline_source0_data;                                                             // agent_pipeline:out_data -> hps_0_f2h_axi_slave_agent:write_cp_data
	wire    [1:0] agent_pipeline_source0_channel;                                                          // agent_pipeline:out_channel -> hps_0_f2h_axi_slave_agent:write_cp_channel
	wire          agent_pipeline_source0_ready;                                                            // hps_0_f2h_axi_slave_agent:write_cp_ready -> agent_pipeline:out_ready
	wire          width_adapter_001_src_endofpacket;                                                       // width_adapter_001:out_endofpacket -> agent_pipeline_001:in_endofpacket
	wire          width_adapter_001_src_valid;                                                             // width_adapter_001:out_valid -> agent_pipeline_001:in_valid
	wire          width_adapter_001_src_startofpacket;                                                     // width_adapter_001:out_startofpacket -> agent_pipeline_001:in_startofpacket
	wire  [227:0] width_adapter_001_src_data;                                                              // width_adapter_001:out_data -> agent_pipeline_001:in_data
	wire          width_adapter_001_src_ready;                                                             // agent_pipeline_001:in_ready -> width_adapter_001:out_ready
	wire    [1:0] width_adapter_001_src_channel;                                                           // width_adapter_001:out_channel -> agent_pipeline_001:in_channel
	wire          agent_pipeline_001_source0_endofpacket;                                                  // agent_pipeline_001:out_endofpacket -> hps_0_f2h_axi_slave_agent:read_cp_endofpacket
	wire          agent_pipeline_001_source0_valid;                                                        // agent_pipeline_001:out_valid -> hps_0_f2h_axi_slave_agent:read_cp_valid
	wire          agent_pipeline_001_source0_startofpacket;                                                // agent_pipeline_001:out_startofpacket -> hps_0_f2h_axi_slave_agent:read_cp_startofpacket
	wire  [227:0] agent_pipeline_001_source0_data;                                                         // agent_pipeline_001:out_data -> hps_0_f2h_axi_slave_agent:read_cp_data
	wire    [1:0] agent_pipeline_001_source0_channel;                                                      // agent_pipeline_001:out_channel -> hps_0_f2h_axi_slave_agent:read_cp_channel
	wire          agent_pipeline_001_source0_ready;                                                        // hps_0_f2h_axi_slave_agent:read_cp_ready -> agent_pipeline_001:out_ready
	wire          hps_0_f2h_axi_slave_agent_write_rp_endofpacket;                                          // hps_0_f2h_axi_slave_agent:write_rp_endofpacket -> agent_pipeline_002:in_endofpacket
	wire          hps_0_f2h_axi_slave_agent_write_rp_valid;                                                // hps_0_f2h_axi_slave_agent:write_rp_valid -> agent_pipeline_002:in_valid
	wire          hps_0_f2h_axi_slave_agent_write_rp_startofpacket;                                        // hps_0_f2h_axi_slave_agent:write_rp_startofpacket -> agent_pipeline_002:in_startofpacket
	wire  [227:0] hps_0_f2h_axi_slave_agent_write_rp_data;                                                 // hps_0_f2h_axi_slave_agent:write_rp_data -> agent_pipeline_002:in_data
	wire          hps_0_f2h_axi_slave_agent_write_rp_ready;                                                // agent_pipeline_002:in_ready -> hps_0_f2h_axi_slave_agent:write_rp_ready
	wire          agent_pipeline_002_source0_endofpacket;                                                  // agent_pipeline_002:out_endofpacket -> id_router:sink_endofpacket
	wire          agent_pipeline_002_source0_valid;                                                        // agent_pipeline_002:out_valid -> id_router:sink_valid
	wire          agent_pipeline_002_source0_startofpacket;                                                // agent_pipeline_002:out_startofpacket -> id_router:sink_startofpacket
	wire  [227:0] agent_pipeline_002_source0_data;                                                         // agent_pipeline_002:out_data -> id_router:sink_data
	wire          agent_pipeline_002_source0_ready;                                                        // id_router:sink_ready -> agent_pipeline_002:out_ready
	wire          hps_0_f2h_axi_slave_agent_read_rp_endofpacket;                                           // hps_0_f2h_axi_slave_agent:read_rp_endofpacket -> agent_pipeline_003:in_endofpacket
	wire          hps_0_f2h_axi_slave_agent_read_rp_valid;                                                 // hps_0_f2h_axi_slave_agent:read_rp_valid -> agent_pipeline_003:in_valid
	wire          hps_0_f2h_axi_slave_agent_read_rp_startofpacket;                                         // hps_0_f2h_axi_slave_agent:read_rp_startofpacket -> agent_pipeline_003:in_startofpacket
	wire  [227:0] hps_0_f2h_axi_slave_agent_read_rp_data;                                                  // hps_0_f2h_axi_slave_agent:read_rp_data -> agent_pipeline_003:in_data
	wire          hps_0_f2h_axi_slave_agent_read_rp_ready;                                                 // agent_pipeline_003:in_ready -> hps_0_f2h_axi_slave_agent:read_rp_ready
	wire          agent_pipeline_003_source0_endofpacket;                                                  // agent_pipeline_003:out_endofpacket -> id_router_001:sink_endofpacket
	wire          agent_pipeline_003_source0_valid;                                                        // agent_pipeline_003:out_valid -> id_router_001:sink_valid
	wire          agent_pipeline_003_source0_startofpacket;                                                // agent_pipeline_003:out_startofpacket -> id_router_001:sink_startofpacket
	wire  [227:0] agent_pipeline_003_source0_data;                                                         // agent_pipeline_003:out_data -> id_router_001:sink_data
	wire          agent_pipeline_003_source0_ready;                                                        // id_router_001:sink_ready -> agent_pipeline_003:out_ready

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (2),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (7),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) alt_vip_vfr_0_avalon_master_translator (
		.clk                      (clk_50_clk_clk),                                                                                                                                                                                                                                                        //                       clk.clk
		.reset                    (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset),                                                                                                                                                                                                          //                     reset.reset
		.uav_address              (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_address),                                                                                                                                                                                              // avalon_universal_master_0.address
		.uav_burstcount           (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_burstcount),                                                                                                                                                                                           //                          .burstcount
		.uav_read                 (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_read),                                                                                                                                                                                                 //                          .read
		.uav_write                (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_write),                                                                                                                                                                                                //                          .write
		.uav_waitrequest          (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_waitrequest),                                                                                                                                                                                          //                          .waitrequest
		.uav_readdatavalid        (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_readdatavalid),                                                                                                                                                                                        //                          .readdatavalid
		.uav_byteenable           (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_byteenable),                                                                                                                                                                                           //                          .byteenable
		.uav_readdata             (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_readdata),                                                                                                                                                                                             //                          .readdata
		.uav_writedata            (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_writedata),                                                                                                                                                                                            //                          .writedata
		.uav_lock                 (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_lock),                                                                                                                                                                                                 //                          .lock
		.uav_debugaccess          (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_debugaccess),                                                                                                                                                                                          //                          .debugaccess
		.av_address               (alt_vip_vfr_0_avalon_master_address),                                                                                                                                                                                                                                   //      avalon_anti_master_0.address
		.av_waitrequest           (alt_vip_vfr_0_avalon_master_waitrequest),                                                                                                                                                                                                                               //                          .waitrequest
		.av_burstcount            (alt_vip_vfr_0_avalon_master_burstcount),                                                                                                                                                                                                                                //                          .burstcount
		.av_read                  (alt_vip_vfr_0_avalon_master_read),                                                                                                                                                                                                                                      //                          .read
		.av_readdata              (alt_vip_vfr_0_avalon_master_readdata),                                                                                                                                                                                                                                  //                          .readdata
		.av_readdatavalid         (alt_vip_vfr_0_avalon_master_readdatavalid),                                                                                                                                                                                                                             //                          .readdatavalid
		.av_byteenable            (32'b11111111111111111111111111111111),                                                                                                                                                                                                                                  //               (terminated)
		.av_beginbursttransfer    (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_begintransfer         (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_chipselect            (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_write                 (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_writedata             (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), //               (terminated)
		.av_lock                  (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_debugaccess           (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.uav_clken                (),                                                                                                                                                                                                                                                                      //               (terminated)
		.av_clken                 (1'b1),                                                                                                                                                                                                                                                                  //               (terminated)
		.uav_response             (2'b00),                                                                                                                                                                                                                                                                 //               (terminated)
		.av_response              (),                                                                                                                                                                                                                                                                      //               (terminated)
		.uav_writeresponserequest (),                                                                                                                                                                                                                                                                      //               (terminated)
		.uav_writeresponsevalid   (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_writeresponserequest  (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_writeresponsevalid    ()                                                                                                                                                                                                                                                                       //               (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (362),
		.PKT_PROTECTION_L          (360),
		.PKT_BEGIN_BURST           (355),
		.PKT_BURSTWRAP_H           (343),
		.PKT_BURSTWRAP_L           (335),
		.PKT_BURST_SIZE_H          (346),
		.PKT_BURST_SIZE_L          (344),
		.PKT_BURST_TYPE_H          (348),
		.PKT_BURST_TYPE_L          (347),
		.PKT_BYTE_CNT_H            (334),
		.PKT_BYTE_CNT_L            (326),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_TRANS_LOCK            (324),
		.PKT_TRANS_EXCLUSIVE       (325),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (357),
		.PKT_SRC_ID_L              (357),
		.PKT_DEST_ID_H             (358),
		.PKT_DEST_ID_L             (358),
		.PKT_THREAD_ID_H           (359),
		.PKT_THREAD_ID_L           (359),
		.PKT_CACHE_H               (366),
		.PKT_CACHE_L               (363),
		.PKT_DATA_SIDEBAND_H       (354),
		.PKT_DATA_SIDEBAND_L       (354),
		.PKT_QOS_H                 (356),
		.PKT_QOS_L                 (356),
		.PKT_ADDR_SIDEBAND_H       (353),
		.PKT_ADDR_SIDEBAND_L       (349),
		.PKT_RESPONSE_STATUS_H     (368),
		.PKT_RESPONSE_STATUS_L     (367),
		.PKT_ORI_BURST_SIZE_L      (369),
		.PKT_ORI_BURST_SIZE_H      (371),
		.ST_DATA_W                 (372),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (7),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (511),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent (
		.clk                     (clk_50_clk_clk),                                                                          //       clk.clk
		.reset                   (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset),                            // clk_reset.reset
		.av_address              (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write                (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read                 (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata            (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata             (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest          (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid        (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable           (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount           (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess          (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock                 (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid                (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data                 (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket        (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket          (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready                (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid                (limiter_rsp_src_valid),                                                                   //        rp.valid
		.rp_data                 (limiter_rsp_src_data),                                                                    //          .data
		.rp_channel              (limiter_rsp_src_channel),                                                                 //          .channel
		.rp_startofpacket        (limiter_rsp_src_startofpacket),                                                           //          .startofpacket
		.rp_endofpacket          (limiter_rsp_src_endofpacket),                                                             //          .endofpacket
		.rp_ready                (limiter_rsp_src_ready),                                                                   //          .ready
		.av_response             (),                                                                                        // (terminated)
		.av_writeresponserequest (1'b0),                                                                                    // (terminated)
		.av_writeresponsevalid   ()                                                                                         // (terminated)
	);

	altera_merlin_axi_slave_ni #(
		.PKT_QOS_H                   (212),
		.PKT_QOS_L                   (212),
		.PKT_THREAD_ID_H             (215),
		.PKT_THREAD_ID_L             (215),
		.PKT_RESPONSE_STATUS_H       (224),
		.PKT_RESPONSE_STATUS_L       (223),
		.PKT_BEGIN_BURST             (211),
		.PKT_CACHE_H                 (222),
		.PKT_CACHE_L                 (219),
		.PKT_DATA_SIDEBAND_H         (210),
		.PKT_DATA_SIDEBAND_L         (210),
		.PKT_ADDR_SIDEBAND_H         (209),
		.PKT_ADDR_SIDEBAND_L         (205),
		.PKT_BURST_TYPE_H            (204),
		.PKT_BURST_TYPE_L            (203),
		.PKT_PROTECTION_H            (218),
		.PKT_PROTECTION_L            (216),
		.PKT_BURST_SIZE_H            (202),
		.PKT_BURST_SIZE_L            (200),
		.PKT_BURSTWRAP_H             (199),
		.PKT_BURSTWRAP_L             (191),
		.PKT_BYTE_CNT_H              (190),
		.PKT_BYTE_CNT_L              (182),
		.PKT_ADDR_H                  (175),
		.PKT_ADDR_L                  (144),
		.PKT_TRANS_EXCLUSIVE         (181),
		.PKT_TRANS_LOCK              (180),
		.PKT_TRANS_COMPRESSED_READ   (176),
		.PKT_TRANS_POSTED            (177),
		.PKT_TRANS_WRITE             (178),
		.PKT_TRANS_READ              (179),
		.PKT_DATA_H                  (127),
		.PKT_DATA_L                  (0),
		.PKT_BYTEEN_H                (143),
		.PKT_BYTEEN_L                (128),
		.PKT_SRC_ID_H                (213),
		.PKT_SRC_ID_L                (213),
		.PKT_DEST_ID_H               (214),
		.PKT_DEST_ID_L               (214),
		.PKT_ORI_BURST_SIZE_L        (225),
		.PKT_ORI_BURST_SIZE_H        (227),
		.ADDR_USER_WIDTH             (5),
		.DATA_USER_WIDTH             (1),
		.ST_DATA_W                   (228),
		.ADDR_WIDTH                  (32),
		.RDATA_WIDTH                 (128),
		.WDATA_WIDTH                 (128),
		.ST_CHANNEL_W                (2),
		.AXI_SLAVE_ID_W              (8),
		.PASS_ID_TO_SLAVE            (1),
		.AXI_VERSION                 ("AXI3"),
		.WRITE_ACCEPTANCE_CAPABILITY (8),
		.READ_ACCEPTANCE_CAPABILITY  (8)
	) hps_0_f2h_axi_slave_agent (
		.aclk                   (pll_sys_outclk0_clk),                                               //        clock_sink.clk
		.aresetn                (~hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), //        reset_sink.reset_n
		.read_cp_valid          (agent_pipeline_001_source0_valid),                                  //           read_cp.valid
		.read_cp_ready          (agent_pipeline_001_source0_ready),                                  //                  .ready
		.read_cp_data           (agent_pipeline_001_source0_data),                                   //                  .data
		.read_cp_channel        (agent_pipeline_001_source0_channel),                                //                  .channel
		.read_cp_startofpacket  (agent_pipeline_001_source0_startofpacket),                          //                  .startofpacket
		.read_cp_endofpacket    (agent_pipeline_001_source0_endofpacket),                            //                  .endofpacket
		.write_cp_ready         (agent_pipeline_source0_ready),                                      //          write_cp.ready
		.write_cp_valid         (agent_pipeline_source0_valid),                                      //                  .valid
		.write_cp_data          (agent_pipeline_source0_data),                                       //                  .data
		.write_cp_channel       (agent_pipeline_source0_channel),                                    //                  .channel
		.write_cp_startofpacket (agent_pipeline_source0_startofpacket),                              //                  .startofpacket
		.write_cp_endofpacket   (agent_pipeline_source0_endofpacket),                                //                  .endofpacket
		.read_rp_ready          (hps_0_f2h_axi_slave_agent_read_rp_ready),                           //           read_rp.ready
		.read_rp_valid          (hps_0_f2h_axi_slave_agent_read_rp_valid),                           //                  .valid
		.read_rp_data           (hps_0_f2h_axi_slave_agent_read_rp_data),                            //                  .data
		.read_rp_startofpacket  (hps_0_f2h_axi_slave_agent_read_rp_startofpacket),                   //                  .startofpacket
		.read_rp_endofpacket    (hps_0_f2h_axi_slave_agent_read_rp_endofpacket),                     //                  .endofpacket
		.write_rp_ready         (hps_0_f2h_axi_slave_agent_write_rp_ready),                          //          write_rp.ready
		.write_rp_valid         (hps_0_f2h_axi_slave_agent_write_rp_valid),                          //                  .valid
		.write_rp_data          (hps_0_f2h_axi_slave_agent_write_rp_data),                           //                  .data
		.write_rp_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket),                  //                  .startofpacket
		.write_rp_endofpacket   (hps_0_f2h_axi_slave_agent_write_rp_endofpacket),                    //                  .endofpacket
		.awid                   (hps_0_f2h_axi_slave_awid),                                          // altera_axi_master.awid
		.awaddr                 (hps_0_f2h_axi_slave_awaddr),                                        //                  .awaddr
		.awlen                  (hps_0_f2h_axi_slave_awlen),                                         //                  .awlen
		.awsize                 (hps_0_f2h_axi_slave_awsize),                                        //                  .awsize
		.awburst                (hps_0_f2h_axi_slave_awburst),                                       //                  .awburst
		.awlock                 (hps_0_f2h_axi_slave_awlock),                                        //                  .awlock
		.awcache                (hps_0_f2h_axi_slave_awcache),                                       //                  .awcache
		.awprot                 (hps_0_f2h_axi_slave_awprot),                                        //                  .awprot
		.awuser                 (hps_0_f2h_axi_slave_awuser),                                        //                  .awuser
		.awvalid                (hps_0_f2h_axi_slave_awvalid),                                       //                  .awvalid
		.awready                (hps_0_f2h_axi_slave_awready),                                       //                  .awready
		.wid                    (hps_0_f2h_axi_slave_wid),                                           //                  .wid
		.wdata                  (hps_0_f2h_axi_slave_wdata),                                         //                  .wdata
		.wstrb                  (hps_0_f2h_axi_slave_wstrb),                                         //                  .wstrb
		.wlast                  (hps_0_f2h_axi_slave_wlast),                                         //                  .wlast
		.wvalid                 (hps_0_f2h_axi_slave_wvalid),                                        //                  .wvalid
		.wready                 (hps_0_f2h_axi_slave_wready),                                        //                  .wready
		.bid                    (hps_0_f2h_axi_slave_bid),                                           //                  .bid
		.bresp                  (hps_0_f2h_axi_slave_bresp),                                         //                  .bresp
		.bvalid                 (hps_0_f2h_axi_slave_bvalid),                                        //                  .bvalid
		.bready                 (hps_0_f2h_axi_slave_bready),                                        //                  .bready
		.arid                   (hps_0_f2h_axi_slave_arid),                                          //                  .arid
		.araddr                 (hps_0_f2h_axi_slave_araddr),                                        //                  .araddr
		.arlen                  (hps_0_f2h_axi_slave_arlen),                                         //                  .arlen
		.arsize                 (hps_0_f2h_axi_slave_arsize),                                        //                  .arsize
		.arburst                (hps_0_f2h_axi_slave_arburst),                                       //                  .arburst
		.arlock                 (hps_0_f2h_axi_slave_arlock),                                        //                  .arlock
		.arcache                (hps_0_f2h_axi_slave_arcache),                                       //                  .arcache
		.arprot                 (hps_0_f2h_axi_slave_arprot),                                        //                  .arprot
		.aruser                 (hps_0_f2h_axi_slave_aruser),                                        //                  .aruser
		.arvalid                (hps_0_f2h_axi_slave_arvalid),                                       //                  .arvalid
		.arready                (hps_0_f2h_axi_slave_arready),                                       //                  .arready
		.rid                    (hps_0_f2h_axi_slave_rid),                                           //                  .rid
		.rdata                  (hps_0_f2h_axi_slave_rdata),                                         //                  .rdata
		.rresp                  (hps_0_f2h_axi_slave_rresp),                                         //                  .rresp
		.rlast                  (hps_0_f2h_axi_slave_rlast),                                         //                  .rlast
		.rvalid                 (hps_0_f2h_axi_slave_rvalid),                                        //                  .rvalid
		.rready                 (hps_0_f2h_axi_slave_rready)                                         //                  .rready
	);

	DE1_SoC_QSYS_mm_interconnect_1_addr_router addr_router (
		.sink_ready         (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (alt_vip_vfr_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (clk_50_clk_clk),                                                                          //       clk.clk
		.reset              (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset),                            // clk_reset.reset
		.src_ready          (addr_router_src_ready),                                                                   //       src.ready
		.src_valid          (addr_router_src_valid),                                                                   //          .valid
		.src_data           (addr_router_src_data),                                                                    //          .data
		.src_channel        (addr_router_src_channel),                                                                 //          .channel
		.src_startofpacket  (addr_router_src_startofpacket),                                                           //          .startofpacket
		.src_endofpacket    (addr_router_src_endofpacket)                                                              //          .endofpacket
	);

	DE1_SoC_QSYS_mm_interconnect_1_id_router id_router (
		.sink_ready         (agent_pipeline_002_source0_ready),                                 //      sink.ready
		.sink_valid         (agent_pipeline_002_source0_valid),                                 //          .valid
		.sink_data          (agent_pipeline_002_source0_data),                                  //          .data
		.sink_startofpacket (agent_pipeline_002_source0_startofpacket),                         //          .startofpacket
		.sink_endofpacket   (agent_pipeline_002_source0_endofpacket),                           //          .endofpacket
		.clk                (pll_sys_outclk0_clk),                                              //       clk.clk
		.reset              (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (id_router_src_ready),                                              //       src.ready
		.src_valid          (id_router_src_valid),                                              //          .valid
		.src_data           (id_router_src_data),                                               //          .data
		.src_channel        (id_router_src_channel),                                            //          .channel
		.src_startofpacket  (id_router_src_startofpacket),                                      //          .startofpacket
		.src_endofpacket    (id_router_src_endofpacket)                                         //          .endofpacket
	);

	DE1_SoC_QSYS_mm_interconnect_1_id_router id_router_001 (
		.sink_ready         (agent_pipeline_003_source0_ready),                                 //      sink.ready
		.sink_valid         (agent_pipeline_003_source0_valid),                                 //          .valid
		.sink_data          (agent_pipeline_003_source0_data),                                  //          .data
		.sink_startofpacket (agent_pipeline_003_source0_startofpacket),                         //          .startofpacket
		.sink_endofpacket   (agent_pipeline_003_source0_endofpacket),                           //          .endofpacket
		.clk                (pll_sys_outclk0_clk),                                              //       clk.clk
		.reset              (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (id_router_001_src_ready),                                          //       src.ready
		.src_valid          (id_router_001_src_valid),                                          //          .valid
		.src_data           (id_router_001_src_data),                                           //          .data
		.src_channel        (id_router_001_src_channel),                                        //          .channel
		.src_startofpacket  (id_router_001_src_startofpacket),                                  //          .startofpacket
		.src_endofpacket    (id_router_001_src_endofpacket)                                     //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (358),
		.PKT_DEST_ID_L             (358),
		.PKT_SRC_ID_H              (357),
		.PKT_SRC_ID_L              (357),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.MAX_OUTSTANDING_RESPONSES (28),
		.PIPELINED                 (0),
		.ST_DATA_W                 (372),
		.ST_CHANNEL_W              (2),
		.VALID_WIDTH               (1),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (1),
		.PKT_BYTE_CNT_H            (334),
		.PKT_BYTE_CNT_L            (326),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.REORDER                   (0)
	) limiter (
		.clk                    (clk_50_clk_clk),                                               //       clk.clk
		.reset                  (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.cmd_sink_ready         (addr_router_src_ready),                                        //  cmd_sink.ready
		.cmd_sink_valid         (addr_router_src_valid),                                        //          .valid
		.cmd_sink_data          (addr_router_src_data),                                         //          .data
		.cmd_sink_channel       (addr_router_src_channel),                                      //          .channel
		.cmd_sink_startofpacket (addr_router_src_startofpacket),                                //          .startofpacket
		.cmd_sink_endofpacket   (addr_router_src_endofpacket),                                  //          .endofpacket
		.cmd_src_ready          (limiter_cmd_src_ready),                                        //   cmd_src.ready
		.cmd_src_data           (limiter_cmd_src_data),                                         //          .data
		.cmd_src_channel        (limiter_cmd_src_channel),                                      //          .channel
		.cmd_src_startofpacket  (limiter_cmd_src_startofpacket),                                //          .startofpacket
		.cmd_src_endofpacket    (limiter_cmd_src_endofpacket),                                  //          .endofpacket
		.cmd_src_valid          (limiter_cmd_src_valid),                                        //          .valid
		.rsp_sink_ready         (limiter_pipeline_001_source0_ready),                           //  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_001_source0_valid),                           //          .valid
		.rsp_sink_channel       (limiter_pipeline_001_source0_channel),                         //          .channel
		.rsp_sink_data          (limiter_pipeline_001_source0_data),                            //          .data
		.rsp_sink_startofpacket (limiter_pipeline_001_source0_startofpacket),                   //          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_001_source0_endofpacket),                     //          .endofpacket
		.rsp_src_ready          (limiter_rsp_src_ready),                                        //   rsp_src.ready
		.rsp_src_valid          (limiter_rsp_src_valid),                                        //          .valid
		.rsp_src_data           (limiter_rsp_src_data),                                         //          .data
		.rsp_src_channel        (limiter_rsp_src_channel),                                      //          .channel
		.rsp_src_startofpacket  (limiter_rsp_src_startofpacket),                                //          .startofpacket
		.rsp_src_endofpacket    (limiter_rsp_src_endofpacket)                                   //          .endofpacket
	);

	DE1_SoC_QSYS_mm_interconnect_1_cmd_xbar_demux cmd_xbar_demux (
		.clk                (clk_50_clk_clk),                                               //       clk.clk
		.reset              (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (limiter_pipeline_source0_ready),                               //      sink.ready
		.sink_channel       (limiter_pipeline_source0_channel),                             //          .channel
		.sink_data          (limiter_pipeline_source0_data),                                //          .data
		.sink_startofpacket (limiter_pipeline_source0_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (limiter_pipeline_source0_endofpacket),                         //          .endofpacket
		.sink_valid         (limiter_pipeline_source0_valid),                               //          .valid
		.src0_ready         (cmd_xbar_demux_src0_ready),                                    //      src0.ready
		.src0_valid         (cmd_xbar_demux_src0_valid),                                    //          .valid
		.src0_data          (cmd_xbar_demux_src0_data),                                     //          .data
		.src0_channel       (cmd_xbar_demux_src0_channel),                                  //          .channel
		.src0_startofpacket (cmd_xbar_demux_src0_startofpacket),                            //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_src0_endofpacket),                              //          .endofpacket
		.src1_ready         (cmd_xbar_demux_src1_ready),                                    //      src1.ready
		.src1_valid         (cmd_xbar_demux_src1_valid),                                    //          .valid
		.src1_data          (cmd_xbar_demux_src1_data),                                     //          .data
		.src1_channel       (cmd_xbar_demux_src1_channel),                                  //          .channel
		.src1_startofpacket (cmd_xbar_demux_src1_startofpacket),                            //          .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_src1_endofpacket)                               //          .endofpacket
	);

	DE1_SoC_QSYS_mm_interconnect_1_cmd_xbar_mux cmd_xbar_mux (
		.clk                 (pll_sys_outclk0_clk),                                              //       clk.clk
		.reset               (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_src_ready),                                           //       src.ready
		.src_valid           (cmd_xbar_mux_src_valid),                                           //          .valid
		.src_data            (cmd_xbar_mux_src_data),                                            //          .data
		.src_channel         (cmd_xbar_mux_src_channel),                                         //          .channel
		.src_startofpacket   (cmd_xbar_mux_src_startofpacket),                                   //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_src_endofpacket),                                     //          .endofpacket
		.sink0_ready         (crosser_out_ready),                                                //     sink0.ready
		.sink0_valid         (crosser_out_valid),                                                //          .valid
		.sink0_channel       (crosser_out_channel),                                              //          .channel
		.sink0_data          (crosser_out_data),                                                 //          .data
		.sink0_startofpacket (crosser_out_startofpacket),                                        //          .startofpacket
		.sink0_endofpacket   (crosser_out_endofpacket)                                           //          .endofpacket
	);

	DE1_SoC_QSYS_mm_interconnect_1_cmd_xbar_mux cmd_xbar_mux_001 (
		.clk                 (pll_sys_outclk0_clk),                                              //       clk.clk
		.reset               (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_001_src_ready),                                       //       src.ready
		.src_valid           (cmd_xbar_mux_001_src_valid),                                       //          .valid
		.src_data            (cmd_xbar_mux_001_src_data),                                        //          .data
		.src_channel         (cmd_xbar_mux_001_src_channel),                                     //          .channel
		.src_startofpacket   (cmd_xbar_mux_001_src_startofpacket),                               //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_001_src_endofpacket),                                 //          .endofpacket
		.sink0_ready         (crosser_001_out_ready),                                            //     sink0.ready
		.sink0_valid         (crosser_001_out_valid),                                            //          .valid
		.sink0_channel       (crosser_001_out_channel),                                          //          .channel
		.sink0_data          (crosser_001_out_data),                                             //          .data
		.sink0_startofpacket (crosser_001_out_startofpacket),                                    //          .startofpacket
		.sink0_endofpacket   (crosser_001_out_endofpacket)                                       //          .endofpacket
	);

	DE1_SoC_QSYS_mm_interconnect_1_rsp_xbar_demux rsp_xbar_demux (
		.clk                (pll_sys_outclk0_clk),                                              //       clk.clk
		.reset              (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (width_adapter_002_src_ready),                                      //      sink.ready
		.sink_channel       (width_adapter_002_src_channel),                                    //          .channel
		.sink_data          (width_adapter_002_src_data),                                       //          .data
		.sink_startofpacket (width_adapter_002_src_startofpacket),                              //          .startofpacket
		.sink_endofpacket   (width_adapter_002_src_endofpacket),                                //          .endofpacket
		.sink_valid         (width_adapter_002_src_valid),                                      //          .valid
		.src0_ready         (rsp_xbar_demux_src0_ready),                                        //      src0.ready
		.src0_valid         (rsp_xbar_demux_src0_valid),                                        //          .valid
		.src0_data          (rsp_xbar_demux_src0_data),                                         //          .data
		.src0_channel       (rsp_xbar_demux_src0_channel),                                      //          .channel
		.src0_startofpacket (rsp_xbar_demux_src0_startofpacket),                                //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_src0_endofpacket)                                   //          .endofpacket
	);

	DE1_SoC_QSYS_mm_interconnect_1_rsp_xbar_demux rsp_xbar_demux_001 (
		.clk                (pll_sys_outclk0_clk),                                              //       clk.clk
		.reset              (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (width_adapter_003_src_ready),                                      //      sink.ready
		.sink_channel       (width_adapter_003_src_channel),                                    //          .channel
		.sink_data          (width_adapter_003_src_data),                                       //          .data
		.sink_startofpacket (width_adapter_003_src_startofpacket),                              //          .startofpacket
		.sink_endofpacket   (width_adapter_003_src_endofpacket),                                //          .endofpacket
		.sink_valid         (width_adapter_003_src_valid),                                      //          .valid
		.src0_ready         (rsp_xbar_demux_001_src0_ready),                                    //      src0.ready
		.src0_valid         (rsp_xbar_demux_001_src0_valid),                                    //          .valid
		.src0_data          (rsp_xbar_demux_001_src0_data),                                     //          .data
		.src0_channel       (rsp_xbar_demux_001_src0_channel),                                  //          .channel
		.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket),                            //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_001_src0_endofpacket)                               //          .endofpacket
	);

	DE1_SoC_QSYS_mm_interconnect_1_rsp_xbar_mux rsp_xbar_mux (
		.clk                 (clk_50_clk_clk),                                               //       clk.clk
		.reset               (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_xbar_mux_src_ready),                                       //       src.ready
		.src_valid           (rsp_xbar_mux_src_valid),                                       //          .valid
		.src_data            (rsp_xbar_mux_src_data),                                        //          .data
		.src_channel         (rsp_xbar_mux_src_channel),                                     //          .channel
		.src_startofpacket   (rsp_xbar_mux_src_startofpacket),                               //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_src_endofpacket),                                 //          .endofpacket
		.sink0_ready         (crosser_002_out_ready),                                        //     sink0.ready
		.sink0_valid         (crosser_002_out_valid),                                        //          .valid
		.sink0_channel       (crosser_002_out_channel),                                      //          .channel
		.sink0_data          (crosser_002_out_data),                                         //          .data
		.sink0_startofpacket (crosser_002_out_startofpacket),                                //          .startofpacket
		.sink0_endofpacket   (crosser_002_out_endofpacket),                                  //          .endofpacket
		.sink1_ready         (crosser_003_out_ready),                                        //     sink1.ready
		.sink1_valid         (crosser_003_out_valid),                                        //          .valid
		.sink1_channel       (crosser_003_out_channel),                                      //          .channel
		.sink1_data          (crosser_003_out_data),                                         //          .data
		.sink1_startofpacket (crosser_003_out_startofpacket),                                //          .startofpacket
		.sink1_endofpacket   (crosser_003_out_endofpacket)                                   //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (319),
		.IN_PKT_ADDR_L                 (288),
		.IN_PKT_DATA_H                 (255),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (287),
		.IN_PKT_BYTEEN_L               (256),
		.IN_PKT_BYTE_CNT_H             (334),
		.IN_PKT_BYTE_CNT_L             (326),
		.IN_PKT_TRANS_COMPRESSED_READ  (320),
		.IN_PKT_BURSTWRAP_H            (343),
		.IN_PKT_BURSTWRAP_L            (335),
		.IN_PKT_BURST_SIZE_H           (346),
		.IN_PKT_BURST_SIZE_L           (344),
		.IN_PKT_RESPONSE_STATUS_H      (368),
		.IN_PKT_RESPONSE_STATUS_L      (367),
		.IN_PKT_TRANS_EXCLUSIVE        (325),
		.IN_PKT_BURST_TYPE_H           (348),
		.IN_PKT_BURST_TYPE_L           (347),
		.IN_PKT_ORI_BURST_SIZE_L       (369),
		.IN_PKT_ORI_BURST_SIZE_H       (371),
		.IN_ST_DATA_W                  (372),
		.OUT_PKT_ADDR_H                (175),
		.OUT_PKT_ADDR_L                (144),
		.OUT_PKT_DATA_H                (127),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (143),
		.OUT_PKT_BYTEEN_L              (128),
		.OUT_PKT_BYTE_CNT_H            (190),
		.OUT_PKT_BYTE_CNT_L            (182),
		.OUT_PKT_TRANS_COMPRESSED_READ (176),
		.OUT_PKT_BURST_SIZE_H          (202),
		.OUT_PKT_BURST_SIZE_L          (200),
		.OUT_PKT_RESPONSE_STATUS_H     (224),
		.OUT_PKT_RESPONSE_STATUS_L     (223),
		.OUT_PKT_TRANS_EXCLUSIVE       (181),
		.OUT_PKT_BURST_TYPE_H          (204),
		.OUT_PKT_BURST_TYPE_L          (203),
		.OUT_PKT_ORI_BURST_SIZE_L      (225),
		.OUT_PKT_ORI_BURST_SIZE_H      (227),
		.OUT_ST_DATA_W                 (228),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0)
	) width_adapter (
		.clk                  (pll_sys_outclk0_clk),                                              //       clk.clk
		.reset                (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (cmd_xbar_mux_src_valid),                                           //      sink.valid
		.in_channel           (cmd_xbar_mux_src_channel),                                         //          .channel
		.in_startofpacket     (cmd_xbar_mux_src_startofpacket),                                   //          .startofpacket
		.in_endofpacket       (cmd_xbar_mux_src_endofpacket),                                     //          .endofpacket
		.in_ready             (cmd_xbar_mux_src_ready),                                           //          .ready
		.in_data              (cmd_xbar_mux_src_data),                                            //          .data
		.out_endofpacket      (width_adapter_src_endofpacket),                                    //       src.endofpacket
		.out_data             (width_adapter_src_data),                                           //          .data
		.out_channel          (width_adapter_src_channel),                                        //          .channel
		.out_valid            (width_adapter_src_valid),                                          //          .valid
		.out_ready            (width_adapter_src_ready),                                          //          .ready
		.out_startofpacket    (width_adapter_src_startofpacket),                                  //          .startofpacket
		.in_command_size_data (3'b000)                                                            // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (319),
		.IN_PKT_ADDR_L                 (288),
		.IN_PKT_DATA_H                 (255),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (287),
		.IN_PKT_BYTEEN_L               (256),
		.IN_PKT_BYTE_CNT_H             (334),
		.IN_PKT_BYTE_CNT_L             (326),
		.IN_PKT_TRANS_COMPRESSED_READ  (320),
		.IN_PKT_BURSTWRAP_H            (343),
		.IN_PKT_BURSTWRAP_L            (335),
		.IN_PKT_BURST_SIZE_H           (346),
		.IN_PKT_BURST_SIZE_L           (344),
		.IN_PKT_RESPONSE_STATUS_H      (368),
		.IN_PKT_RESPONSE_STATUS_L      (367),
		.IN_PKT_TRANS_EXCLUSIVE        (325),
		.IN_PKT_BURST_TYPE_H           (348),
		.IN_PKT_BURST_TYPE_L           (347),
		.IN_PKT_ORI_BURST_SIZE_L       (369),
		.IN_PKT_ORI_BURST_SIZE_H       (371),
		.IN_ST_DATA_W                  (372),
		.OUT_PKT_ADDR_H                (175),
		.OUT_PKT_ADDR_L                (144),
		.OUT_PKT_DATA_H                (127),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (143),
		.OUT_PKT_BYTEEN_L              (128),
		.OUT_PKT_BYTE_CNT_H            (190),
		.OUT_PKT_BYTE_CNT_L            (182),
		.OUT_PKT_TRANS_COMPRESSED_READ (176),
		.OUT_PKT_BURST_SIZE_H          (202),
		.OUT_PKT_BURST_SIZE_L          (200),
		.OUT_PKT_RESPONSE_STATUS_H     (224),
		.OUT_PKT_RESPONSE_STATUS_L     (223),
		.OUT_PKT_TRANS_EXCLUSIVE       (181),
		.OUT_PKT_BURST_TYPE_H          (204),
		.OUT_PKT_BURST_TYPE_L          (203),
		.OUT_PKT_ORI_BURST_SIZE_L      (225),
		.OUT_PKT_ORI_BURST_SIZE_H      (227),
		.OUT_ST_DATA_W                 (228),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0)
	) width_adapter_001 (
		.clk                  (pll_sys_outclk0_clk),                                              //       clk.clk
		.reset                (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (cmd_xbar_mux_001_src_valid),                                       //      sink.valid
		.in_channel           (cmd_xbar_mux_001_src_channel),                                     //          .channel
		.in_startofpacket     (cmd_xbar_mux_001_src_startofpacket),                               //          .startofpacket
		.in_endofpacket       (cmd_xbar_mux_001_src_endofpacket),                                 //          .endofpacket
		.in_ready             (cmd_xbar_mux_001_src_ready),                                       //          .ready
		.in_data              (cmd_xbar_mux_001_src_data),                                        //          .data
		.out_endofpacket      (width_adapter_001_src_endofpacket),                                //       src.endofpacket
		.out_data             (width_adapter_001_src_data),                                       //          .data
		.out_channel          (width_adapter_001_src_channel),                                    //          .channel
		.out_valid            (width_adapter_001_src_valid),                                      //          .valid
		.out_ready            (width_adapter_001_src_ready),                                      //          .ready
		.out_startofpacket    (width_adapter_001_src_startofpacket),                              //          .startofpacket
		.in_command_size_data (3'b000)                                                            // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (175),
		.IN_PKT_ADDR_L                 (144),
		.IN_PKT_DATA_H                 (127),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (143),
		.IN_PKT_BYTEEN_L               (128),
		.IN_PKT_BYTE_CNT_H             (190),
		.IN_PKT_BYTE_CNT_L             (182),
		.IN_PKT_TRANS_COMPRESSED_READ  (176),
		.IN_PKT_BURSTWRAP_H            (199),
		.IN_PKT_BURSTWRAP_L            (191),
		.IN_PKT_BURST_SIZE_H           (202),
		.IN_PKT_BURST_SIZE_L           (200),
		.IN_PKT_RESPONSE_STATUS_H      (224),
		.IN_PKT_RESPONSE_STATUS_L      (223),
		.IN_PKT_TRANS_EXCLUSIVE        (181),
		.IN_PKT_BURST_TYPE_H           (204),
		.IN_PKT_BURST_TYPE_L           (203),
		.IN_PKT_ORI_BURST_SIZE_L       (225),
		.IN_PKT_ORI_BURST_SIZE_H       (227),
		.IN_ST_DATA_W                  (228),
		.OUT_PKT_ADDR_H                (319),
		.OUT_PKT_ADDR_L                (288),
		.OUT_PKT_DATA_H                (255),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (287),
		.OUT_PKT_BYTEEN_L              (256),
		.OUT_PKT_BYTE_CNT_H            (334),
		.OUT_PKT_BYTE_CNT_L            (326),
		.OUT_PKT_TRANS_COMPRESSED_READ (320),
		.OUT_PKT_BURST_SIZE_H          (346),
		.OUT_PKT_BURST_SIZE_L          (344),
		.OUT_PKT_RESPONSE_STATUS_H     (368),
		.OUT_PKT_RESPONSE_STATUS_L     (367),
		.OUT_PKT_TRANS_EXCLUSIVE       (325),
		.OUT_PKT_BURST_TYPE_H          (348),
		.OUT_PKT_BURST_TYPE_L          (347),
		.OUT_PKT_ORI_BURST_SIZE_L      (369),
		.OUT_PKT_ORI_BURST_SIZE_H      (371),
		.OUT_ST_DATA_W                 (372),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1)
	) width_adapter_002 (
		.clk                  (pll_sys_outclk0_clk),                                              //       clk.clk
		.reset                (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (id_router_src_valid),                                              //      sink.valid
		.in_channel           (id_router_src_channel),                                            //          .channel
		.in_startofpacket     (id_router_src_startofpacket),                                      //          .startofpacket
		.in_endofpacket       (id_router_src_endofpacket),                                        //          .endofpacket
		.in_ready             (id_router_src_ready),                                              //          .ready
		.in_data              (id_router_src_data),                                               //          .data
		.out_endofpacket      (width_adapter_002_src_endofpacket),                                //       src.endofpacket
		.out_data             (width_adapter_002_src_data),                                       //          .data
		.out_channel          (width_adapter_002_src_channel),                                    //          .channel
		.out_valid            (width_adapter_002_src_valid),                                      //          .valid
		.out_ready            (width_adapter_002_src_ready),                                      //          .ready
		.out_startofpacket    (width_adapter_002_src_startofpacket),                              //          .startofpacket
		.in_command_size_data (3'b000)                                                            // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (175),
		.IN_PKT_ADDR_L                 (144),
		.IN_PKT_DATA_H                 (127),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (143),
		.IN_PKT_BYTEEN_L               (128),
		.IN_PKT_BYTE_CNT_H             (190),
		.IN_PKT_BYTE_CNT_L             (182),
		.IN_PKT_TRANS_COMPRESSED_READ  (176),
		.IN_PKT_BURSTWRAP_H            (199),
		.IN_PKT_BURSTWRAP_L            (191),
		.IN_PKT_BURST_SIZE_H           (202),
		.IN_PKT_BURST_SIZE_L           (200),
		.IN_PKT_RESPONSE_STATUS_H      (224),
		.IN_PKT_RESPONSE_STATUS_L      (223),
		.IN_PKT_TRANS_EXCLUSIVE        (181),
		.IN_PKT_BURST_TYPE_H           (204),
		.IN_PKT_BURST_TYPE_L           (203),
		.IN_PKT_ORI_BURST_SIZE_L       (225),
		.IN_PKT_ORI_BURST_SIZE_H       (227),
		.IN_ST_DATA_W                  (228),
		.OUT_PKT_ADDR_H                (319),
		.OUT_PKT_ADDR_L                (288),
		.OUT_PKT_DATA_H                (255),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (287),
		.OUT_PKT_BYTEEN_L              (256),
		.OUT_PKT_BYTE_CNT_H            (334),
		.OUT_PKT_BYTE_CNT_L            (326),
		.OUT_PKT_TRANS_COMPRESSED_READ (320),
		.OUT_PKT_BURST_SIZE_H          (346),
		.OUT_PKT_BURST_SIZE_L          (344),
		.OUT_PKT_RESPONSE_STATUS_H     (368),
		.OUT_PKT_RESPONSE_STATUS_L     (367),
		.OUT_PKT_TRANS_EXCLUSIVE       (325),
		.OUT_PKT_BURST_TYPE_H          (348),
		.OUT_PKT_BURST_TYPE_L          (347),
		.OUT_PKT_ORI_BURST_SIZE_L      (369),
		.OUT_PKT_ORI_BURST_SIZE_H      (371),
		.OUT_ST_DATA_W                 (372),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1)
	) width_adapter_003 (
		.clk                  (pll_sys_outclk0_clk),                                              //       clk.clk
		.reset                (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (id_router_001_src_valid),                                          //      sink.valid
		.in_channel           (id_router_001_src_channel),                                        //          .channel
		.in_startofpacket     (id_router_001_src_startofpacket),                                  //          .startofpacket
		.in_endofpacket       (id_router_001_src_endofpacket),                                    //          .endofpacket
		.in_ready             (id_router_001_src_ready),                                          //          .ready
		.in_data              (id_router_001_src_data),                                           //          .data
		.out_endofpacket      (width_adapter_003_src_endofpacket),                                //       src.endofpacket
		.out_data             (width_adapter_003_src_data),                                       //          .data
		.out_channel          (width_adapter_003_src_channel),                                    //          .channel
		.out_valid            (width_adapter_003_src_valid),                                      //          .valid
		.out_ready            (width_adapter_003_src_ready),                                      //          .ready
		.out_startofpacket    (width_adapter_003_src_startofpacket),                              //          .startofpacket
		.in_command_size_data (3'b000)                                                            // (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (372),
		.BITS_PER_SYMBOL     (372),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser (
		.in_clk            (clk_50_clk_clk),                                                   //        in_clk.clk
		.in_reset          (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset),     //  in_clk_reset.reset
		.out_clk           (pll_sys_outclk0_clk),                                              //       out_clk.clk
		.out_reset         (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (cmd_xbar_demux_src0_ready),                                        //            in.ready
		.in_valid          (cmd_xbar_demux_src0_valid),                                        //              .valid
		.in_startofpacket  (cmd_xbar_demux_src0_startofpacket),                                //              .startofpacket
		.in_endofpacket    (cmd_xbar_demux_src0_endofpacket),                                  //              .endofpacket
		.in_channel        (cmd_xbar_demux_src0_channel),                                      //              .channel
		.in_data           (cmd_xbar_demux_src0_data),                                         //              .data
		.out_ready         (crosser_out_ready),                                                //           out.ready
		.out_valid         (crosser_out_valid),                                                //              .valid
		.out_startofpacket (crosser_out_startofpacket),                                        //              .startofpacket
		.out_endofpacket   (crosser_out_endofpacket),                                          //              .endofpacket
		.out_channel       (crosser_out_channel),                                              //              .channel
		.out_data          (crosser_out_data),                                                 //              .data
		.in_empty          (1'b0),                                                             //   (terminated)
		.in_error          (1'b0),                                                             //   (terminated)
		.out_empty         (),                                                                 //   (terminated)
		.out_error         ()                                                                  //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (372),
		.BITS_PER_SYMBOL     (372),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_001 (
		.in_clk            (clk_50_clk_clk),                                                   //        in_clk.clk
		.in_reset          (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset),     //  in_clk_reset.reset
		.out_clk           (pll_sys_outclk0_clk),                                              //       out_clk.clk
		.out_reset         (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (cmd_xbar_demux_src1_ready),                                        //            in.ready
		.in_valid          (cmd_xbar_demux_src1_valid),                                        //              .valid
		.in_startofpacket  (cmd_xbar_demux_src1_startofpacket),                                //              .startofpacket
		.in_endofpacket    (cmd_xbar_demux_src1_endofpacket),                                  //              .endofpacket
		.in_channel        (cmd_xbar_demux_src1_channel),                                      //              .channel
		.in_data           (cmd_xbar_demux_src1_data),                                         //              .data
		.out_ready         (crosser_001_out_ready),                                            //           out.ready
		.out_valid         (crosser_001_out_valid),                                            //              .valid
		.out_startofpacket (crosser_001_out_startofpacket),                                    //              .startofpacket
		.out_endofpacket   (crosser_001_out_endofpacket),                                      //              .endofpacket
		.out_channel       (crosser_001_out_channel),                                          //              .channel
		.out_data          (crosser_001_out_data),                                             //              .data
		.in_empty          (1'b0),                                                             //   (terminated)
		.in_error          (1'b0),                                                             //   (terminated)
		.out_empty         (),                                                                 //   (terminated)
		.out_error         ()                                                                  //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (372),
		.BITS_PER_SYMBOL     (372),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_002 (
		.in_clk            (pll_sys_outclk0_clk),                                              //        in_clk.clk
		.in_reset          (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (clk_50_clk_clk),                                                   //       out_clk.clk
		.out_reset         (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset),     // out_clk_reset.reset
		.in_ready          (rsp_xbar_demux_src0_ready),                                        //            in.ready
		.in_valid          (rsp_xbar_demux_src0_valid),                                        //              .valid
		.in_startofpacket  (rsp_xbar_demux_src0_startofpacket),                                //              .startofpacket
		.in_endofpacket    (rsp_xbar_demux_src0_endofpacket),                                  //              .endofpacket
		.in_channel        (rsp_xbar_demux_src0_channel),                                      //              .channel
		.in_data           (rsp_xbar_demux_src0_data),                                         //              .data
		.out_ready         (crosser_002_out_ready),                                            //           out.ready
		.out_valid         (crosser_002_out_valid),                                            //              .valid
		.out_startofpacket (crosser_002_out_startofpacket),                                    //              .startofpacket
		.out_endofpacket   (crosser_002_out_endofpacket),                                      //              .endofpacket
		.out_channel       (crosser_002_out_channel),                                          //              .channel
		.out_data          (crosser_002_out_data),                                             //              .data
		.in_empty          (1'b0),                                                             //   (terminated)
		.in_error          (1'b0),                                                             //   (terminated)
		.out_empty         (),                                                                 //   (terminated)
		.out_error         ()                                                                  //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (372),
		.BITS_PER_SYMBOL     (372),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_003 (
		.in_clk            (pll_sys_outclk0_clk),                                              //        in_clk.clk
		.in_reset          (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (clk_50_clk_clk),                                                   //       out_clk.clk
		.out_reset         (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset),     // out_clk_reset.reset
		.in_ready          (rsp_xbar_demux_001_src0_ready),                                    //            in.ready
		.in_valid          (rsp_xbar_demux_001_src0_valid),                                    //              .valid
		.in_startofpacket  (rsp_xbar_demux_001_src0_startofpacket),                            //              .startofpacket
		.in_endofpacket    (rsp_xbar_demux_001_src0_endofpacket),                              //              .endofpacket
		.in_channel        (rsp_xbar_demux_001_src0_channel),                                  //              .channel
		.in_data           (rsp_xbar_demux_001_src0_data),                                     //              .data
		.out_ready         (crosser_003_out_ready),                                            //           out.ready
		.out_valid         (crosser_003_out_valid),                                            //              .valid
		.out_startofpacket (crosser_003_out_startofpacket),                                    //              .startofpacket
		.out_endofpacket   (crosser_003_out_endofpacket),                                      //              .endofpacket
		.out_channel       (crosser_003_out_channel),                                          //              .channel
		.out_data          (crosser_003_out_data),                                             //              .data
		.in_empty          (1'b0),                                                             //   (terminated)
		.in_error          (1'b0),                                                             //   (terminated)
		.out_empty         (),                                                                 //   (terminated)
		.out_error         ()                                                                  //   (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (372),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline (
		.clk               (clk_50_clk_clk),                                               //       cr0.clk
		.reset             (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (limiter_cmd_src_ready),                                        //     sink0.ready
		.in_valid          (limiter_cmd_src_valid),                                        //          .valid
		.in_startofpacket  (limiter_cmd_src_startofpacket),                                //          .startofpacket
		.in_endofpacket    (limiter_cmd_src_endofpacket),                                  //          .endofpacket
		.in_data           (limiter_cmd_src_data),                                         //          .data
		.in_channel        (limiter_cmd_src_channel),                                      //          .channel
		.out_ready         (limiter_pipeline_source0_ready),                               //   source0.ready
		.out_valid         (limiter_pipeline_source0_valid),                               //          .valid
		.out_startofpacket (limiter_pipeline_source0_startofpacket),                       //          .startofpacket
		.out_endofpacket   (limiter_pipeline_source0_endofpacket),                         //          .endofpacket
		.out_data          (limiter_pipeline_source0_data),                                //          .data
		.out_channel       (limiter_pipeline_source0_channel),                             //          .channel
		.in_empty          (1'b0),                                                         // (terminated)
		.out_empty         (),                                                             // (terminated)
		.out_error         (),                                                             // (terminated)
		.in_error          (1'b0)                                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (372),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline_001 (
		.clk               (clk_50_clk_clk),                                               //       cr0.clk
		.reset             (alt_vip_vfr_0_clock_master_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (rsp_xbar_mux_src_ready),                                       //     sink0.ready
		.in_valid          (rsp_xbar_mux_src_valid),                                       //          .valid
		.in_startofpacket  (rsp_xbar_mux_src_startofpacket),                               //          .startofpacket
		.in_endofpacket    (rsp_xbar_mux_src_endofpacket),                                 //          .endofpacket
		.in_data           (rsp_xbar_mux_src_data),                                        //          .data
		.in_channel        (rsp_xbar_mux_src_channel),                                     //          .channel
		.out_ready         (limiter_pipeline_001_source0_ready),                           //   source0.ready
		.out_valid         (limiter_pipeline_001_source0_valid),                           //          .valid
		.out_startofpacket (limiter_pipeline_001_source0_startofpacket),                   //          .startofpacket
		.out_endofpacket   (limiter_pipeline_001_source0_endofpacket),                     //          .endofpacket
		.out_data          (limiter_pipeline_001_source0_data),                            //          .data
		.out_channel       (limiter_pipeline_001_source0_channel),                         //          .channel
		.in_empty          (1'b0),                                                         // (terminated)
		.out_empty         (),                                                             // (terminated)
		.out_error         (),                                                             // (terminated)
		.in_error          (1'b0)                                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (228),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline (
		.clk               (pll_sys_outclk0_clk),                                              //       cr0.clk
		.reset             (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (width_adapter_src_ready),                                          //     sink0.ready
		.in_valid          (width_adapter_src_valid),                                          //          .valid
		.in_startofpacket  (width_adapter_src_startofpacket),                                  //          .startofpacket
		.in_endofpacket    (width_adapter_src_endofpacket),                                    //          .endofpacket
		.in_data           (width_adapter_src_data),                                           //          .data
		.in_channel        (width_adapter_src_channel),                                        //          .channel
		.out_ready         (agent_pipeline_source0_ready),                                     //   source0.ready
		.out_valid         (agent_pipeline_source0_valid),                                     //          .valid
		.out_startofpacket (agent_pipeline_source0_startofpacket),                             //          .startofpacket
		.out_endofpacket   (agent_pipeline_source0_endofpacket),                               //          .endofpacket
		.out_data          (agent_pipeline_source0_data),                                      //          .data
		.out_channel       (agent_pipeline_source0_channel),                                   //          .channel
		.in_empty          (1'b0),                                                             // (terminated)
		.out_empty         (),                                                                 // (terminated)
		.out_error         (),                                                                 // (terminated)
		.in_error          (1'b0)                                                              // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (228),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_001 (
		.clk               (pll_sys_outclk0_clk),                                              //       cr0.clk
		.reset             (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (width_adapter_001_src_ready),                                      //     sink0.ready
		.in_valid          (width_adapter_001_src_valid),                                      //          .valid
		.in_startofpacket  (width_adapter_001_src_startofpacket),                              //          .startofpacket
		.in_endofpacket    (width_adapter_001_src_endofpacket),                                //          .endofpacket
		.in_data           (width_adapter_001_src_data),                                       //          .data
		.in_channel        (width_adapter_001_src_channel),                                    //          .channel
		.out_ready         (agent_pipeline_001_source0_ready),                                 //   source0.ready
		.out_valid         (agent_pipeline_001_source0_valid),                                 //          .valid
		.out_startofpacket (agent_pipeline_001_source0_startofpacket),                         //          .startofpacket
		.out_endofpacket   (agent_pipeline_001_source0_endofpacket),                           //          .endofpacket
		.out_data          (agent_pipeline_001_source0_data),                                  //          .data
		.out_channel       (agent_pipeline_001_source0_channel),                               //          .channel
		.in_empty          (1'b0),                                                             // (terminated)
		.out_empty         (),                                                                 // (terminated)
		.out_error         (),                                                                 // (terminated)
		.in_error          (1'b0)                                                              // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (228),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_002 (
		.clk               (pll_sys_outclk0_clk),                                              //       cr0.clk
		.reset             (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (hps_0_f2h_axi_slave_agent_write_rp_ready),                         //     sink0.ready
		.in_valid          (hps_0_f2h_axi_slave_agent_write_rp_valid),                         //          .valid
		.in_startofpacket  (hps_0_f2h_axi_slave_agent_write_rp_startofpacket),                 //          .startofpacket
		.in_endofpacket    (hps_0_f2h_axi_slave_agent_write_rp_endofpacket),                   //          .endofpacket
		.in_data           (hps_0_f2h_axi_slave_agent_write_rp_data),                          //          .data
		.out_ready         (agent_pipeline_002_source0_ready),                                 //   source0.ready
		.out_valid         (agent_pipeline_002_source0_valid),                                 //          .valid
		.out_startofpacket (agent_pipeline_002_source0_startofpacket),                         //          .startofpacket
		.out_endofpacket   (agent_pipeline_002_source0_endofpacket),                           //          .endofpacket
		.out_data          (agent_pipeline_002_source0_data),                                  //          .data
		.in_empty          (1'b0),                                                             // (terminated)
		.out_empty         (),                                                                 // (terminated)
		.out_error         (),                                                                 // (terminated)
		.in_error          (1'b0),                                                             // (terminated)
		.out_channel       (),                                                                 // (terminated)
		.in_channel        (1'b0)                                                              // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (228),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_003 (
		.clk               (pll_sys_outclk0_clk),                                              //       cr0.clk
		.reset             (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (hps_0_f2h_axi_slave_agent_read_rp_ready),                          //     sink0.ready
		.in_valid          (hps_0_f2h_axi_slave_agent_read_rp_valid),                          //          .valid
		.in_startofpacket  (hps_0_f2h_axi_slave_agent_read_rp_startofpacket),                  //          .startofpacket
		.in_endofpacket    (hps_0_f2h_axi_slave_agent_read_rp_endofpacket),                    //          .endofpacket
		.in_data           (hps_0_f2h_axi_slave_agent_read_rp_data),                           //          .data
		.out_ready         (agent_pipeline_003_source0_ready),                                 //   source0.ready
		.out_valid         (agent_pipeline_003_source0_valid),                                 //          .valid
		.out_startofpacket (agent_pipeline_003_source0_startofpacket),                         //          .startofpacket
		.out_endofpacket   (agent_pipeline_003_source0_endofpacket),                           //          .endofpacket
		.out_data          (agent_pipeline_003_source0_data),                                  //          .data
		.in_empty          (1'b0),                                                             // (terminated)
		.out_empty         (),                                                                 // (terminated)
		.out_error         (),                                                                 // (terminated)
		.in_error          (1'b0),                                                             // (terminated)
		.out_channel       (),                                                                 // (terminated)
		.in_channel        (1'b0)                                                              // (terminated)
	);

endmodule
