# TCL File Generated by Component Editor 13.0dp
# Fri Jul 26 10:34:18 CST 2013
# DO NOT MODIFY


# 
# TERASIC_LOOPBACK "TERASIC_LOOPBACK" v1.0
#  2013.07.26.10:34:18
# 
# 

# 
# request TCL package from ACDS 13.0
# 
package require -exact qsys 13.0


# 
# module TERASIC_LOOPBACK
# 
set_module_property DESCRIPTION ""
set_module_property NAME TERASIC_LOOPBACK
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Terasic Qsys Component/"
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME TERASIC_LOOPBACK
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false


# 
# file sets
# 
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL TERASIC_LOOPBACK
set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file TERASIC_LOOPBACK.v VERILOG PATH TERASIC_LOOPBACK.v TOP_LEVEL_FILE


# 
# parameters
# 
add_parameter PAIR_NUM INTEGER 32 ""
set_parameter_property PAIR_NUM DEFAULT_VALUE 32
set_parameter_property PAIR_NUM DISPLAY_NAME PAIR_NUM
set_parameter_property PAIR_NUM TYPE INTEGER
set_parameter_property PAIR_NUM UNITS None
set_parameter_property PAIR_NUM ALLOWED_RANGES -2147483648:2147483647
set_parameter_property PAIR_NUM DESCRIPTION ""
set_parameter_property PAIR_NUM AFFECTS_GENERATION false
set_parameter_property PAIR_NUM HDL_PARAMETER true
add_parameter PAIR_BIR INTEGER 1
set_parameter_property PAIR_BIR DEFAULT_VALUE 1
set_parameter_property PAIR_BIR DISPLAY_NAME PAIR_BIR
set_parameter_property PAIR_BIR TYPE INTEGER
set_parameter_property PAIR_BIR UNITS None
set_parameter_property PAIR_BIR ALLOWED_RANGES -2147483648:2147483647
set_parameter_property PAIR_BIR AFFECTS_GENERATION false
set_parameter_property PAIR_BIR HDL_PARAMETER true


# 
# display items
# 


# 
# connection point slave
# 
add_interface slave avalon end
set_interface_property slave addressAlignment NATIVE
set_interface_property slave addressUnits WORDS
set_interface_property slave associatedClock clk
set_interface_property slave associatedReset reset_n
set_interface_property slave bitsPerSymbol 8
set_interface_property slave burstOnBurstBoundariesOnly false
set_interface_property slave burstcountUnits WORDS
set_interface_property slave explicitAddressSpan 0
set_interface_property slave holdTime 0
set_interface_property slave linewrapBursts false
set_interface_property slave maximumPendingReadTransactions 0
set_interface_property slave readLatency 0
set_interface_property slave readWaitTime 1
set_interface_property slave setupTime 0
set_interface_property slave timingUnits Cycles
set_interface_property slave writeWaitTime 0
set_interface_property slave ENABLED true
set_interface_property slave EXPORT_OF ""
set_interface_property slave PORT_NAME_MAP ""
set_interface_property slave SVD_ADDRESS_GROUP ""

add_interface_port slave s_cs chipselect Input 1
add_interface_port slave s_read read Input 1
add_interface_port slave s_readdata readdata Output PAIR_NUM
add_interface_port slave s_write write Input 1
add_interface_port slave s_writedata writedata Input PAIR_NUM
set_interface_assignment slave embeddedsw.configuration.isFlash 0
set_interface_assignment slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment slave embeddedsw.configuration.isPrintableDevice 0


# 
# connection point reset_n
# 
add_interface reset_n reset end
set_interface_property reset_n associatedClock clk
set_interface_property reset_n synchronousEdges DEASSERT
set_interface_property reset_n ENABLED true
set_interface_property reset_n EXPORT_OF ""
set_interface_property reset_n PORT_NAME_MAP ""
set_interface_property reset_n SVD_ADDRESS_GROUP ""

add_interface_port reset_n reset_n reset_n Input 1


# 
# connection point clk
# 
add_interface clk clock end
set_interface_property clk clockRate 0
set_interface_property clk ENABLED true
set_interface_property clk EXPORT_OF ""
set_interface_property clk PORT_NAME_MAP ""
set_interface_property clk SVD_ADDRESS_GROUP ""

add_interface_port clk clk clk Input 1


# 
# connection point conduit
# 
add_interface conduit conduit end
set_interface_property conduit associatedClock ""
set_interface_property conduit associatedReset ""
set_interface_property conduit ENABLED true
set_interface_property conduit EXPORT_OF ""
set_interface_property conduit PORT_NAME_MAP ""
set_interface_property conduit SVD_ADDRESS_GROUP ""

add_interface_port conduit lb_in export Bidir PAIR_NUM
add_interface_port conduit lb_out export Bidir PAIR_NUM

