// ============================================================================
// Copyright (c) 2014 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development
//   Kits made by Terasic.  Other use of this code, including the selling
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use
//   or functionality of this code.
//
// ============================================================================
//
//  Terasic Technologies Inc
//  9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
//                     web: http://www.terasic.com/
//                     email: support@terasic.com
//
// ============================================================================
//Date:  Fri Oct 24 14:09:29 2014
// ============================================================================

//`define ENABLE_DDR3
`define ENABLE_SD
`define ENABLE_USB


module DECA_golden_top(

      ///////// ADC /////////
      input              ADC_CLK_10,

`ifdef ENABLE_AUDIO
      ///////// AUDIO /////////
      inout              AUDIO_BCLK,
      output             AUDIO_DIN_MFP1,
      input              AUDIO_DOUT_MFP2,
      inout              AUDIO_GPIO_MFP5,
      output             AUDIO_MCLK,
      input              AUDIO_MISO_MFP4,
      inout              AUDIO_RESET_n,
      output             AUDIO_SCLK_MFP3,
      output             AUDIO_SCL_SS_n,
      inout              AUDIO_SDA_MOSI,
      output             AUDIO_SPI_SELECT,
      inout              AUDIO_WCLK,
`endif /*ENABLE_AUDIO*/

`ifdef ENABLE_CAP_TOUCH
      ///////// CAP /////////
      inout              CAP_SENSE_I2C_SCL,
      inout              CAP_SENSE_I2C_SDA,
`endif /* ENABLE_CAP_TOUCH */

`ifdef ENABLE_DDR3
      ///////// DDR3 /////////
      output      [14:0] DDR3_A,
      output      [2:0]  DDR3_BA,
      output             DDR3_CAS_n,
      output             DDR3_CKE,
      inout             DDR3_CK_n,
      inout             DDR3_CK_p,
      input              DDR3_CLK_50,
      output             DDR3_CS_n,
      output      [1:0]  DDR3_DM,
      inout       [15:0] DDR3_DQ,
      inout       [1:0]  DDR3_DQS_n,
      inout       [1:0]  DDR3_DQS_p,
      output             DDR3_ODT,
      output             DDR3_RAS_n,
      output             DDR3_RESET_n,
      output             DDR3_WE_n,
`endif /*ENABLE_DDR3*/

`ifdef ENABLE_SFLASH
      ///////// FLASH /////////
      inout       [3:0]  FLASH_DATA,
      output             FLASH_DCLK,
      output             FLASH_NCSO,
      output             FLASH_RESET_n,
`endif /* ENABLE_SFLASH */

`ifdef ENABLE_GPIO
      ///////// GPIO0 /////////
      inout       [43:0] GPIO0_D,

      ///////// GPIO1 /////////
      inout       [22:0] GPIO1_D,
`endif /* GPIO */

      ///////// GSENSOR /////////
      output             GSENSOR_PD,
      output             GSENSOR_ST,

`ifdef ENABLE_HDMI
      ///////// HDMI /////////
      inout              HDMI_I2C_SCL,
      inout              HDMI_I2C_SDA,
      inout       [3:0]  HDMI_I2S,
      inout              HDMI_LRCLK,
      inout              HDMI_MCLK,
      inout              HDMI_SCLK,
      output             HDMI_TX_CLK,
      output      [23:0] HDMI_TX_D,
      output             HDMI_TX_DE,
      output             HDMI_TX_HS,
      input              HDMI_TX_INT,
      output             HDMI_TX_VS,
`endif /*HDMI*/

      ///////// KEY /////////
      input       [1:0]  KEY,

      ///////// LED /////////
      output      [7:0]  LED,

      ///////// LIGHT /////////
      output             LIGHT_I2C_SCL,
      inout              LIGHT_I2C_SDA,
      inout              LIGHT_INT,

      ///////// MAX10 /////////
      input              MAX10_CLK1_50,
      input              MAX10_CLK2_50,

`ifdef ENABLE_MIPI
      ///////// MIPI /////////
      output             MIPI_CORE_EN,
      output             MIPI_I2C_SCL,
      inout              MIPI_I2C_SDA,
      input              MIPI_LP_MC_n,
      input              MIPI_LP_MC_p,
      input       [3:0]  MIPI_LP_MD_n,
      input       [3:0]  MIPI_LP_MD_p,
      output             MIPI_MCLK,
      input              MIPI_MC_p,
      input       [3:0]  MIPI_MD_p,
      output             MIPI_RESET_n,
      output             MIPI_WP,
`endif /* ENABLE_MIPI */

`ifdef ENABLE_ENET
      ///////// NET /////////
      input              NET_COL,
      input              NET_CRS,
      output             NET_MDC,
      inout              NET_MDIO,
      output             NET_PCF_EN,
      output             NET_RESET_n,
      input       [3:0]  NET_RXD,
      input              NET_RX_CLK,
      input              NET_RX_DV,
      input              NET_RX_ER,
      output      [3:0]  NET_TXD,
      input              NET_TX_CLK,
      output             NET_TX_EN,
`endif /* ENABLE_ENET */

      ///////// PMONITOR /////////
      input              PMONITOR_ALERT,
      output             PMONITOR_I2C_SCL,
      inout              PMONITOR_I2C_SDA,

      ///////// BBB /////////
      input              BBB_PWR_BUT,

      ///////// RH /////////
      input              RH_TEMP_DRDY_n,
      output             RH_TEMP_I2C_SCL,
      inout              RH_TEMP_I2C_SDA,

`ifdef ENABLE_SD
      ///////// SD /////////
      output             SD_CLK,
      inout              SD_CMD,
      output             SD_CMD_DIR,
      output             SD_D0_DIR,
      output             SD_D123_DIR,
      inout       [3:0]  SD_DAT,
      input              SD_FB_CLK,
      output             SD_SEL,
`endif /* ENABLE_SD */

      ///////// SW /////////
      input       [1:0]  SW,


      ///////// TEMP /////////
      output             TEMP_CS_n,
      output             TEMP_SC,
      inout              TEMP_SIO,

`ifdef ENABLE_USB
      ///////// USB /////////
      input              USB_CLKIN,     //Phy OUTPUT 60Mhz Clock 
//      output             USB_CLKOUT,
//      output             USB_CLKOUT_NOPLL, // was: Phy output USB_CLKOUT_NOPLL,
      output             USB_CS,
      inout       [7:0]  USB_DATA,
      input              USB_DIR,
      input              USB_FAULT_n,
      input              USB_NXT,
      output             USB_RESET_n,
      output             USB_STP,
`endif /* ENABLE_USB */

      ///////// BBB /////////
      input              BBB_SYS_RESET_n
);


//=======================================================
//  REG/WIRE declarations
//=======================================================
wire           ext_reset_pio; // Software controlled reset
wire           usb_phy_cs_n;
wire           usb_phy_reset_n;   //Active Low

assign         USB_CS = 1'b1; // ~usb_phy_cs_n;
assign         USB_RESET_n = usb_phy_reset_n | KEY[1];

wire           usb_clk_input_60M;
wire           pll_locked;
wire           ddr3_intial_done;

wire     [7:0] user_led_pio;
wire           usb_clk_60;

//=======================================================
//  Structural coding
//=======================================================

usb_pll u1(
   .areset(~KEY[0]),
   .inclk0(USB_CLKIN),
	.c0(usb_clk_input_60M),
	.locked(pll_locked)

);

    usb20sr_refdes u0 (
    
        //Clk and Reset
        
        .osc_clk_clk                         (MAX10_CLK1_50),                                      
        .reset_reset_n                       (1'b1         ),                                             
        .altpll_0_areset_conduit_export      (1'b0         ),                                               
        .altpll_0_locked_conduit_export      (             ),                                                   
        .altpll_0_phasedone_conduit_export   (             ),                                                      
        .usb_clk_60_pll_c1_clk               (usb_clk_60),   //Not used as far -- SLS
        
          
        //USB2.0 SR 
		  .u20_clk_out_clk                     (usb_clk_input_60M),
        .usb20sr_conduit_end_Data            (USB_DATA     ),                                           
        .usb20sr_conduit_end_Stp             (USB_STP      ),                                            
        .usb20sr_conduit_end_Dir             (USB_DIR      ),                                            
        .usb20sr_conduit_end_Nxt             (USB_NXT      ),                                            
        .usb20sr_conduit_end_phy_clk         (usb_clk_input_60M    ),                                          
        .usb20sr_conduit_end_phy_reset_n     (usb_phy_reset_n  ),                                        
        .usb20sr_conduit_end_phy_cs_n        (usb_phy_cs_n ),                                       
        .usb20sr_conduit_end_Ext_reset_in    (1'b0),    //used  -- Terasic

        //SDHC 
        
        .sdhc_conduit_end_SD_CLK             (SD_CLK       ),           
        .sdhc_conduit_end_SD_CMD             (SD_CMD       ),    
        .sdhc_conduit_end_SD_DAT0            (SD_DAT[0]    ),    
        .sdhc_conduit_end_SD_DAT1            (SD_DAT[1]    ),    
        .sdhc_conduit_end_SD_DAT2            (SD_DAT[2]    ),    
        .sdhc_conduit_end_SD_DAT3            (SD_DAT[3]    ),    
        .sdhc_conduit_end_SD_IN              (1'b1         ),    
        .sdhc_conduit_end_SD_WP              (1'b0         ),    
        .sdhc_conduit_end_SD_BUSY            (             ),    
        .sdhc_conduit_end_SD_EMMC_VCC_EN     (             ),  
        .sdhc_conduit_end_EMMC_VCC_Q_EN      (             ),  
        .sdhc_conduit_end_SD_VOLTAGE_SEL     (SD_SEL       ),  
        .sdhc_conduit_end_SD_CMD_DIR         (SD_CMD_DIR   ),  
        .sdhc_conduit_end_SD_DATA0_DIR       (SD_D0_DIR    ),  
        .sdhc_conduit_end_SD_DATA123_DIR     (SD_D123_DIR  ),  
        .sdhc_conduit_end_SD_CLK_FB          (SD_FB_CLK    ),

         
         // DDR3
`ifdef ENABLE_DDR3
		  .mem_if_ddr3_emif_0_pll_ref_clk_clk          (DDR3_CLK_50),
        .memory_mem_a                                (DDR3_A),
        .memory_mem_ba                               (DDR3_BA),
        .memory_mem_ck                               (DDR3_CK_p),
        .memory_mem_ck_n                             (DDR3_CK_n),
        .memory_mem_cke                              (DDR3_CKE),
        .memory_mem_cs_n                             (DDR3_CS_n),
        .memory_mem_dm                               (DDR3_DM),
        .memory_mem_ras_n                            (DDR3_RAS_n),
        .memory_mem_cas_n                            (DDR3_CAS_n),
        .memory_mem_we_n                             (DDR3_WE_n),
        .memory_mem_reset_n                          (DDR3_RESET_n),
        .memory_mem_dq                               (DDR3_DQ),
        .memory_mem_dqs                              (DDR3_DQS_p),
        .memory_mem_dqs_n                            (DDR3_DQS_n),
        .memory_mem_odt                              (DDR3_ODT),
          
        .mem_if_ddr3_emif_0_status_local_init_done       (ddr3_intial_done),
        .mem_if_ddr3_emif_0_status_local_cal_success     (),
        .mem_if_ddr3_emif_0_status_local_cal_fail        (),
        .mem_if_ddr3_emif_0_pll_sharing_pll_mem_clk      (),
        .mem_if_ddr3_emif_0_pll_sharing_pll_write_clk    (),
        .mem_if_ddr3_emif_0_pll_sharing_pll_locked       (),
        .mem_if_ddr3_emif_0_pll_sharing_pll_capture0_clk (),
        .mem_if_ddr3_emif_0_pll_sharing_pll_capture1_clk (),
`endif /*ENABLE_DDR3*/          
        //GPIO
        
        .rst_pio_external_connection_export  (ext_reset_pio),                                      
        .user_led_external_connection_export (user_led_pio )                                                
        
    );
    
//    assign LED = ~user_led_pio;
assign LED[0] = ~pll_locked;
assign LED[1] = ~ddr3_intial_done;
assign LED[7:2] = 7'b1111111;



endmodule
