<?xml version="1.0" encoding="UTF-8"?>
<preferences>
 <debug showDebugMenu="0" />
 <systemtable filter="All Interfaces" showClockDomains="0" showResetDomains="0">
  <columns>
   <connections preferredWidth="335" />
   <irq preferredWidth="47" />
   <inputclock preferredWidth="247" />
   <description preferredWidth="382" />
  </columns>
 </systemtable>
 <library expandedCategories="Project,Library" />
 <window width="1874" height="1096" x="54" y="-8" />
 <hdlexample language="VERILOG" />
</preferences>
